Device Modeling

Publications: 2006 2005 2004 2003 2002 2001 2000 1999 1998 1997 1996 1995 1994 1993 1985 1984

2006

• Model Dispersive Media in Finite-Difference Time-Domain Method with Complex-Conjugate Pole-Residue Pairs IEEE Microwave and Wireless Components Letters, Vol. 16, 3, p.119-121, March 2006
  -Han, Dutton Fan
  • Text {PDF}

• Modeling of charge trapping induced threshold voltage instabilities in high-k gate dielectric FETs," IEEE Electron Dev. Lett., Vol. 27, p.489-491, 2006
  -Liu, Shanware, Colombo, Dutton
  • Text {PDF}

2005

• Mode-locking of monolithic laser diodes incorporating coupled-resonator optical waveguides," Optics Express, Vol. 13, p.4539-4553, 2005
  -Liu, Wang, Han, Fan, Dutton
  • Text {PDF}

• Effects of Local Electric Field and Effective Tunnel Mass on the Simulation of Band-to-band Tunnel Diode Model (SISPAD 2005, Sept. 2005)
  -Kim, Dutton

• Metallic photonic crystals with strong broadband absorption at optical frequencies over with wide angular range (Journal of Applied Physics, April 2005)
  -Veronis, Dutton, Fan
  • Text {PDF}

• Minimum Achievable Phase Noise of RC Oscillators (IEEE Journals of Solid-State Circuits, Vol. 40, No.3, pp.630-637, March 2005)
  -Navid, Lee, Dutton
  • Text {PDF}

• An Analytical Formulation of Phase Noise of Signals with Gaussian-Distributed Jitter (IEEE Transactions on Circuits and Systems II, Vol. 52, No. 3, pp. 149-153, March 2005)
  -Navid, Lee, Dutton
  • Text {PDF}

• Monte Carlo Simulation of Joule Heating in Bulk and Strained Silicon (Applied Physics Letters, 86, (9), Feb. 2005)
  -Pop, Dutton, Goodson
  • Text {PDF}

• Coupled optical and electronic simulations of electrically pumped photonic-crystal-based light emitting diodes (Journal of Applied Physics, 97, Feb. 2005)
  -Veronis, Suh, Liu, Han, Wang, Dutton, Fan
  • Text {PDF}

• A new method for sensitivity analysis of photonic crystal devices (SPIE Proceeding Series, 5733, 2005)
  -Veronis, Dutton, Fan
  • Text {PDF}

• Coupled optical and electronic simulations of electrically pumped photonic-crystal-based LEDs (SPIE Proceeding Series, 5733 2005)
  -Veronis, Liu, Suh, Han, Wang, Dutton, Fan
  • Text {PDF}

2004

• Electro-Thermal Characteristics of Strained-Si MOSFETs in High-Current Operation (Transactions on Electron Devices, Vol. 51, (11), Nov. 2004)
  -Choi,Chun, Dutton
  • Text {PDF}

• Technology Limits and compact model for SiGe Scaled FETs (presentation at NanoTech Conference - MSM 2004)
  -Dutton, Choi
  • Text {PDF}

• Electro-Thermal Comparison and Performance Optimization of Thin-Body SOI and GOI MOSFETs (IEDM, Dec. 2004, San Francisco, CA)
  -Pop, Chui, Sinha, Dutton, Goodson
  • Text {PDF}

• Analytic Band Monte Carlo Model for Electron Transport in Si Including Acoustic and Optical Phonon Dispersion (J. Appl. Phys. Vol. 96, No. 9, Nov. 2004)
  -Pop, Goodson, Dutton
  • Text {PDF}

• Compact Modeling and Experimental Verification of Substrate Resistance in Lightly Doped Substrates (SASIMI' 04, Kanazawa, Japan Oct 18-19, 2004 , pp. 189 - 195)
  -Lan, Chen, Chui, Dutton
  • Text {PDF}

• Realization of Digital Noise Emulator for Characterization of Systems Exposed to Substrate Noise (SASIMI' 04, Kanazawa, Japan Oct 18-19, 2004, pp. 196 - 203)
  -Lu, Kim, Nakano, Colleran, Yue, Dutton
  • Text {PDF}

• Method for sensitivity analysis of photonic crystal devices (Optics Letters, 29, Oct. 2004, pp.2288-2290)
  -Veronis, Dutton, Fan
  • Text {PDF}

• Electro-thermal Simulations of Strained-Si MOSFETs under ESD conditions (SISPAD, Sept. 2004)
  -Chun, Choi, Dutton
  • Text {PDF}

• Effects of scaling on the SNR and speed of biosensors (EMBS, Sept. 2004, San Francisco, CA)
  -Hassibi, Lee, Navid, Dutton, Zahedi
  • Text {PDF}

• Statistical modeling of biochemical detection systems (EMBS, Sept. 2004, San Francisco, CA)
  -Zahedi, Navid, Hassibi
  • Text {PDF}

• A comprehensive study of noise processes in electrode-electrolyte interfaces (Journal of Applied Physics, Vol 96 (2), pp. 1074-1082. July 15, 2004)
  -Hassibi, Navid, Dutton, Lee
  • Text {PDF}

• Close-in Phase Noise in Electrical Oscillators (SPIE Conference of Fluctuations and Noise, May 2004, Canary Islands, Spain)
  -Navid, Jungemann, Lee, Dutton
  • Text {PDF}

• A PMOSFET ESD Failure Caused by Localized Charge Injection (IRPS '04, April 2004)
  -Chun, Duvvury, Boselli, Kunz, Dutton
  • Text {PDF}

• Modeling of Wave Behavior of Substrate Noise Coupling for Mixed-signal IC Design (ISQED, March 2004)
  -Veronis, Lu, Dutton
  • Text {PDF}

• Synthesized Compact Models (SCM) of Substrate Noise Coupling Analysis and Synthesis in Mixed-Signal ICs (DATE '04, Feb. 2004)
  -Lan, Dutton
  • Text {PDF}

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2003

• Resonant Gate Tunneling Current in Double-Gate SOI: A Simulation Study (IEEE Trans. Electron Devices, Vol. 50, pp. 2579-2581, Dec. 2003)
  -Choi, Yu, Dutton
  • Text {PDF}

• Implementation of Temperature Depdendent Contact Resistance Model for the Analysis of Deep Submicron devices under ESD (IEDM, Dec. 2003, Washington DC)
  -Chun, Liu, Duvvury, Dutton
  • Text {PDF}

• Thermal Analysis of Ultra-Thin Body Device Scaling (IEDM, Dec. 2003, Washington DC)
  -Pop, Goodson, Dutton
  • Text {PDF}

• Lumped, Inductorless Oscillators: How Far Can They Go? (CICC, Sept. 2003)
  -Navid, Lee, Dutton
  • Text {PDF}

• Characterization of Zener-Tunneling Drain Leakage Current in High-Dose Halo Implants (SISPAD, Sept. 2003)
  -Choi, Yang, Pollack, Ekbote, Chidambaram, Johnson, Machala, Dutton
  • Text {PDF}

• Investigation of Thermal Breakdown Mechanism in 0.13 um Technology ggNMOS under ESD Conditions (SISPAD, Sept. 2003)
  -Hillkirk, Chun, Dutton
  • Text {PDF}

• Hydrodynamic Simulation of RF Noise in Deep-Submicron MOSFETs (SISPAD, Sept. 2003)
  -Oh, Jungemann, Dutton
  • Text {PDF}

• Detailed Heat Generation Simulations via the Monte Carlo Method (SISPAD, Sept. 2003, Boston MA)
  -Pop, Goodson, Dutton
  • Text {PDF}

• Monte Carlo Simulation of Heat Generation in Silicon Nano-Devices (SRC TechCon, Aug. 2003, Dallas TX)
  -Pop, Goodson, Dutton
• Modeling of Temperature Dependent Contact Resistance for Analysis of ESD Reliability (Proceedings of International Reliability Physics Symposium 2003, pp. 226-234)
  -Oh, Chun, Banerjee, Duvvury, Dutton
  • Text {PDF}

• Impact of Poly-Gate Depletion on MOS RF Linearity (IEEE Electron Device Letters, vol.24, pp. 330-332, May 2003)
  -Choi, Yu, Dutton
  • Text {PDF}

• Behavioral Simulation Techniques for Substrate Noise Analysis in PLL Circuits (SASIMI' 03, Hiroshima, Japan, April 2003)
  -Kim, Perrott, Dutton
  • Text {PDF}

• Efficient Techniques for Reducing Complexity of Subtrate Models in Mixed-signal IC's (SASIMI '03, Hiroshima, Japan, April 2003, pp. 83-88)
  -Lan, Lu, Nakano, Dutton
  • Text {PDF}

• A CAD-oriented Modeling Approach of Frequency-dependent Behavior of Substrate Noise Coupling for Mixed-signal IC Design (ISQED '03, San Jose, CA, March 2003, pp.195-200)
  -Lan, Yu, Dutton
  • Text {PDF}

• Compact Modeling and Design Using Ultra-thin SOI Devices-Implications of Gate Tunneling and Quantum Effects (2003 NanoTech, Feb. 2003)
  -Dutton, Choi
  • Text {PDF}

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2002

• Non-uniform Conduction Induced Reverse Channel Length Dependence of ESD Reliability for Silicided NMOS Transistors (IEDM '02. Dec. 2002, pp 341-344)
  -Oh,Banerjee, Duvvury, Dutton
  • Text {PDF}

• Two-Dimensional Polysilicon Quantum-Mechanical Effects in Double-Gate SOI (IEDM, pp. 723-726, Dec. 2002)
  -Choi, Yu, Dutton
  • Text {PDF}

• Impact of Gate-to-contact spacing on ESD Performance of Salicided Deep Submicron NMOS Transistors (IEEE Trans. on Electron Devices, Vol 49, pp. 2183-2192, Dec. 2002)
  -Oh, Duvvury, Banerjee, Dutton
  • Text {PDF}

• Analysis and Design of Distributed ESD Protection Circuits for High-Speed Mixed-Signal and RF ICs (IEEE Trans. on Electron Devices, Vol. 49, No 8, pp. 1444-1454, 2002)
  -Ito, Banerjee, Dutton
  • Text {PDF}

• Performance Improvement in Larger RF LDMOSFET Power Amplifiers (Proc. Asia-Pacific Microwave Conference, 2002)
  -Ito, Fujioka, Yoshida, Dutton
  • Text {PDF}

• Analysis of Nonuniform ESD Current Distribution in Deep Submicron NMOS Transisters (IEEE Trans. on Electron Devices, Vol. 49, pp. 2171-2182, Dec. 2002)
  -Oh, Duvvury, Banerjee, Dutton
  • Text {PDF}

• Impact of Lateral Source/Drain Abruptness on Device Performance (IEEE Trans. on Electron Devices, Vol. 49, pp. 1882-1890, Nov. 2002)
  -Kwong, Kasnavi, Griffin, Plummer, Dutton
  • Text {PDF}

• Monte Carlo Modeling of Heat Generation in Electronic Nanostructures (IMECE, Nov. 2002, New Orleans, LA)
  -Pop, Sinha, Goodson
  • Text {PDF}

• The Physical Phenomena Responsible for Excess noise in Short-Channel MOS Deices (SISPAD, Kobe, Japan, PP 75 -78, September 2002)
  -Navid, Dutton
  • Text {PDF}

• A Noise Optimization Technique for Integrated Low-Noise Amplifiers (IEEE Journal of Solid State Circuits, Vol. 37, No. 8, pp. 994-1002, Aug. 2002)
  -Goo, Ahn, Ladwig, Yu, Lee, Dutton
  • Text {PDF}

• Dopant Profile and Gate Geometric Effects on Polysilicon Gate Depletion in Scaled MOS (IEEE Trans. Electron Devices, Vol. 49, pp. 1227-1231, July 2002)
  -Choi, Chidambaram, Khamankar, Machala, Yu, Dutton
  • Text {PDF}

• Series Resistance Calculation for Source/Drain Extention Using 2-D Device Simulation (IEEE Trans. Electron Devices, Vol. 49, pp. 1219-1226, July 2002)
  -Kwong, Choi, Kasnavi, Griffin, Dutton
  • Text {PDF}

• Gate Length Dependent Polysilicon Depletion Effects (IEEE Electron Device Letters, Vol. 23, pp. 224-226, April 2002)
  -Choi, Chidambaram, Khamankar, Machala, Yu, Dutton
  • Text {PDF}

• Device-Level Simulation of Wave Propagation Along Metal-Insulator-Semiconductor Interconnects (IEEE Trans. on Microwave Theory and Techniques, Vol. 50, No. 4, April 2002)
  -Wang, Dutton, Rafferty
  • Text {PDF}

• Investigation of Gate to Contact Spacing Effect on ESD Robustness of Salicided Deep Submicron Single Finger NMOS Transistors (IRPS, pp. 148-155, Dallas, Texas, April, 2002)
  -Oh, Duvvury, Banerjee, Dutton
  • Text {PDF}

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2001

• Impact of Gate Direct Tunneling Current on Circuit Performance (IEEE Trans. on Electron Devices, Vol. 48, No. 12, pp. 2823-2829, Dec. 2001)
  -Choi, Nam, Yu, Dutton
  • Text {PDF}

• Gate Bias Induced Heating Effect and Implications for the Design of Deep Submicron ESD Protection (IEDM, Washington DC, Dec. 2001)
  -Oh, Duvury, Banerjee, Dutton
  • Text {PDF}
    
  • Slide {PDF}

• Localized Heating Effects and Scaling of Sub-0.18 Micron CMOS Devices (IEDM, Dec. 2001, Washington DC)
  -Pop, Banerjee, Sverdrup, Dutton, Goodson
  • Text {PDF}
    
  • Slide {PPT}

• Impact of Gate Tunneling Current in Scaled MOS on Circuit Performance (SASIMI, pp. 387-393, Nara, Japan, Oct. 2001)
  -Choi, Yu, Dutton
  • Text {PDF}

• Design Methodology for Power-Constrained Low Noise RF Circuits (SASIMI, Nara, Japan, pp. 394-401, Oct. 2001)
  -Goo, Ahn, Ladwig, Yu, Lee, Dutton
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  • Slide {PDF}

• High Frequency Characterization and Modeling of VLSI On-Chip Interconnects (SASIMI, Nara, Japan, Oct. 2001)
  -Qi, Kleveland, Wang, Yu, Wong, Dutton, Furusawa
  • Text {PDF}

• Impact of Substrate Resistance on Drain Current Noise in MOSFETs (SISPAD 2001, Athens, Greece, pp. 182-185, Sept. 2001)
  -Goo, Donati, Choi, Yu, Lee, Dutton
  • Text {PDF}
    
  • Slide {PDF}

• Device Level Modeling of Metal-Insulator-Semiconductor Interconnects (IEEE Transactions on Electron Devices, Vol. 48, No. 8 Aug. 2001, pp. 1672-1682)
  -Wang, Qi, Yu, Dutton
  • Text {PDF}

• First Principles Investigation of Scaling Trends of Zirconium Silicate Interface Band Offsets (Journal of Applied Physics, Vol. 90, No. 3, pp. 1333-1341)
  -Kawamoto, Cho, Griffin, Dutton
  • Text {PDF}

• RF LDMOS Characterization and Its Compact Modeling (2001 IEEE MTT-S International Microwave Symposium Digest, pp. 967-970, May 2001)
  -Jang, Tornblad, Arnborg, Chen, Banerjee, Yu, Dutton
  • Text {PDF}

• A Fast Analytical Technique for Estimating the Bounds of On-Chip Clock Wire Inductance (CICC 2001, May 2001)
  -Lu, Banerjee, Celik, Dutton
  • Text {PDF}

• Non-uniform Bipolar Conduction in Single Finger NMOS Transistors and Implications for Deep Submicron ESD Design (IRPS, Orlando, FL, April 30-May 3, 2001)
  -Oh, Duvvury, Salling, Banerjee, Dutton
  • Text {PDF}

• Fast Placement-Dependent Full Chip Thermal Simulation (Proceedings of 2001 International Symposium on VLSI Technology, Systems, and Applications, pp. 249-252, April 2001, Taipei, Taiwan)
  -Yu, Yergeau, Dutton, Nakagawa, Deeney, Chang, Lin, Xie
  • Text {PDF}

• Analysis and Design of ESD Protection Circuits for High-Frequency/RF Applications (Proc. of ISQED, March 2001)
  -Ito, Banerjee, Dutton
  • Text {PDF}

• Analysis and Optimization of Distributed ESD Protection Circuits for High-Speed Mixed-Signal and RF Applications (Proc. EOS/ESD Symp., pp. 355-363, 2001)
  -Ito, Banerjee, Dutton
  • Text {PDF}

• Physical Origin of the Excess Thermal Noise in Short Channel MOSFETs, (IEEE Electron Device Letters, Vol. 22, No. 2, pp. 101-103, Feb. 2001)
  -Goo, Choi, Abramo, Ahn, Yu, Lee, Dutton
  • Text {PDF}

• Atomic Scale Effects of Zirconium and Hafnium Incorporation at a Model Silicon/Silicate Interface by First Principles Calculations IEEE Electron Device Letters, Vol. 22, No. 1, pp. 14-16, Jan. 2001
  -Kawamoto, Jameson, Griffin, Cho, Dutton
  • Text {PDF}

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2000

• Equivalence of van der Ziel and BSIM4 Models in Modeling the Induced Gate Noise of MOSFETs (Technical Digest of IEDM, pp. 811-814, Dec. 2000)
  -Goo, Liu, Choi, Green, Yu, Lee, Dutton
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  • Slide {PDF}

• An Accurate and Efficient High Frequency Noise Simulation Technique for Deep Submicron MOSFETs (IEEE Trans. on Electron Devices, Vol. 47, No. 12, pp. 2410-2419, Dec. 2000)
  -Goo, Choi, Danneville, Morifuji, Sasaki Momose, Yu, Iwai, Lee, Dutton
  • Text {PDF}

• Perspectives on Technology and Technology-Driven CAD (IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, No. 20, Dec. 2000)
  -Dutton, Strojwas
  • Text {PDF}

• Challenges for Atomic Scale Modeling in Alternative Gate Stack Engineering (IEEE Trans. on Electron Devices, Vol. 47, No. 10, pp. 1787-1794, Oct. 2000)
  -Kawamoto, Jameson, Cho, Dutton
  • Text {PDF}

• Capacitance Reconstruction from Measured C-V in High Leakage, Nitride/Oxide MOS (IEEE Trans. Electron Devices, Vol. 47, pp. 1843 - 1850, Oct. 2000)
  -Choi, Wu, Goo, Yu, Dutton
  • Text {PDF, POSTSCRIPT}

• Circuit/Device Modeling at the Quantum Level (IEEE Trans. on Electron Devices, Vol. 47, No. 10, Oct. 2000)
  -Yu, Dutton, Kiehl
  • Text {PDF}

• Advanced Electro-Thermal Modeling and Simulation Techniques for Deep Sub-Micron Devices (SRC-Techcon 2000, Sep. 2000)
  -Sverdrup, Sinha, Pop, Tornblad, Dutton, Goodson

• Guidelines for the Power Constrained Design of a CMOS Tuned LNA (Proc. SISPAD, pp. 269-272, Sept. 2000)
  -Goo, Oh, Choi, Yu, Lee, Dutton
  • Text {PDF}
  • Slide {PDF}

• Large Signal Analysis of On-Chip Interconnects Using Transport Based Approach (Proc. of ISAPE 2000, pp. 309-312, Aug. 2000, Beijing, China)
  -Wang, Qi, Yu, Dutton, Rafferty
  • Text {PDF}

• A Fast 3-D Modeling Approach to Electrical Parameters Extraction of Bonding Wires for RF (IEEE Trans. on Advanced Packaging, Vol. 23, No. 3, Aug. 2000)
  -Qi, Yue, Arnborg, Soh, Sakai, Yu, Dutton,
  
  • Text {PDF}

• Modeling of MOS Scaling with Emphasis on Gate Tunneling and Source/Drain Resistance (Superlattices and Microstructures, Vol. 27, No. 2/3, 2000)
  -Choi, Yu, Dutton
  • Text {POSTSCRIPT}
    
  • Figures {POSTSCRIPT}

• On-Chip Inductance Modeling and RLC Extraction of VLSI Interconnects for Circuit Simulation (CICC '00, May 2000)
  -Qi, Wang, Yu, Dutton, Young
  • Text {POSTSCRIPT}
  • Slides {PDF, POSTSCRIPT}

• Compact Electrothermal Modeling of RF Power LDMOS (SASIMI, April, 2000)
  -Tornblad, Jang, Qi, Arnborg, Chen, Yu, Dutton

• Process and Layout Dependent Substrate Resistance Modeling for Deep Sub-Micron ESD Protection Devices (IRPS Proceedings, San Jose, CA, April 2000)
  -Zhang, Banerjee, Amerasekera, Gupta, Yu, Dutton
  • Text {PDF}

• Shallow Source/Drain Extension Effects on External Resistance in Sub-0.1µm MOSFET's (IEEE Transactions on Electron Devices, Vol. 47, pp. 655-658, March, 2000)
  -Choi, Goo, Yu, Dutton
  • Text {POSTSCRIPT}

• On-Chip Inductance Modeling of VLSI Interconnects (ISSCC 2000, Feb. 2000)
  -Qi, Kleveland, Yu, Wong, Dutton, Young
  • Text {POSTSCRIPT}
  • Figures {POSTSCRIPT}
  • Slides {POSTSCRIPT}

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1999

• Line Inductance Extraction and Modeling in a Real Chip with Power Grid (IEDM '99 - Dec. 1999)
  -Kleveland, Qi, Madden, Dutton, Wong
  • Text {PDF}

• Direct Tunneling Current Model for Circuit Simulation (IEDM '99 - Dec. 1999)
  -Choi, Oh, Goo, Yu, Dutton
  • Text {PDF, POSTSCRIPT}

• A Bias Dependent Source/Drain Resistance Model in LDD MOSFET Devices for Distortion Analysis (ICVC '99, pp 190-193, Oct. 1999, Seoul, South Korea)
  -Oh, Yu, Dutton
  • Text {PDF}

• A Quasi-Mixed-Mode MOSFET Model for Simulation and Prediction of Substrate Resistance under ESD Stress and Layout Variations (SISPAD '99 - Sept. 1999)
  -Zhang, Yu, Dutton
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• Density-Gradient Analysis of Tunneling in MOS Structures with Ultra-Thin Oxides (SISPAD '99 - Sept. 1999)
  -Ancona, Yu, Dutton, Voorde, Cao, Vook
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• Circuit Model for Power LDMOS Including Quasi-Saturation (SISPAD '99 - Sept. 1999)
  -Jang, Yu, Dutton
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• Issues in High Frequency Noise Simulation for Deep Submicron MOSFETs (International Conference on Unsolved Problems of Noise and Fluctuations (UPoN - July 1999)
  -Goo, Choi, Danneville, Yu, Lee, Dutton
  • Text {PDF}

• RF Noise Simulation for Submicron MOSFET's Based on Hydrodynamic Model (VLSI Symposium - June 1999)
  -Goo, Choi, Morifuji, Momose, Yu, Iwai, Lee, Dutton
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• C-V and Gate Tunneling Current Characterization of Ultra-Thin Gate Oxide MOS (VLSI Symposium - June 1999)
  -Choi, Goo, Oh, Yu, Dutton, Bayoumi, Cao, Voorde, Vook
  • Text {POSTSCRIPT, PDF}
  • Figures {POSTSCRIPT}
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• MOS C-V Characterization of Ultra-Thin Gate Oxide Thickness (1.3-1.8nm) (IEEE Electron Device Letters - June 1999)
  -Choi, Goo, Oh, Yu, Dutton, Bayoumi, Cao, Voorde, Vook
  • Text {POSTSCRIPT}

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1998

• A Fast 3D Modeling Approach to Parasitics Extraction of Bonding Wires for RF Circuits (IEDM '98 - Dec. 1998)
  -Qi, Yue, Arnborg, Soh, Yu, Dutton, Sakai
  • Paper {POSTSCRIPT}
  • Slides {POSTSCRIPT}

• Circuit/Device Modeling at the Quantum Level (Invited Paper) (IWCE-6 1998, pp. 222-229, Oct. 1998, Osaka, Japan)
  -Yu, Dutton, Kiehl
  • Text {PDF}

• Characterization of RF Power BJT and Improvement of Thermal Stability with Nonlinear Base Ballasting (IEEE Journal of Solid-State Circuits, Vol. 33, No. 9, Sept. 1998)
  -Jang, Kan, Arnborg, Johansson, Dutton
  • Text {PDF}

• Multi-dimensional Quantum Effect Simulation Using a Density-Gradient Model and Script-level Programming Techniques (SISPAD '98 - Sept. 1998)
  -Rafferty, Yu, Biegel, Ancona, Bude, Dutton
  • Text {PDF, POSTSCRIPT}

• Layout-based 3D Solid Modeler of IC Structures and Interconnects Including Electrical Parameter Extraction (SISPAD '98 - Sept. 1998)
  -Qi, Shen, Hsiau, Yu, Dutton
  • Text {POSTSCRIPT, PDF}
  • Figures {POSTSCRIPT, PDF}
  • Slides {POSTSCRIPT}

• Design Optimization of RF Power MOSFET's Using Large Signal Analysis Device Simulation of Matching Networks (SISPAD '98 - Sept. 1998)
  -Rotella, Ma, Yu, Dutton
  • Text {POSTSCRIPT, PDF}

• Elimination of Non-Simultaneous Triggering Effects in Finger-type ESD Protection Transistors Using Heterojunction Buried Layer (SISPAD '98 - Sept. 1998)
  -Choi, Yu, Dutton
  • Text {POSTSCRIPT, PDF}

• Modeling and Simulation of an RF LDMOS Device Using Harmonic Balance PISCES (TECHCON '98 - Sept. 1998)
  -Rotella, Ma, Yu, Dutton
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• Substrate Resistance Model for Simulating MOSFET Breakdown in ESD Protection (TECHCON '98 - Sept. 1998)
  -Zhang, Yu, Beebe, Dutton
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1997

• Device Simulation for RF Applications (IEDM '97 - Dec. 1997)
  -Dutton, Troyanovsky, Yu, Arnborg, Rotella, Ma, Sato-Iwanaga
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• Efficient Multi-Tone Harmonic Balance Simulation of Semiconductor Devices in the Presence of Linear High-Q Circuitry (SASIMI '97 - Dec. 1997)
  -Troyanovsky, Rotella, Yu, Dutton, Arborg
  • Text {POSTSCRIPT, PDF}

• Device Modeling and Simulation for VLSI Design (ICVC '97 - October 1997)
  -Dutton

• Robust, Stable, and Accurate Boundary Movement for Physical Etching and Deposition Simulation (IEEE Trans. Elec. Dev. Vol. 44, No. 9, Sept. 1997)
  -Hsiau, Kan, McVittie, Dutton
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• Improved Performance and Thermal Stability of Interdigitated Power RF Bipolar Transistors with Nonlinear Base Ballasting (1997 BCTM Conf. - Sept. 1997)
  -Jang, Kan, Dutton, Arnborg
  • Text {POSTSCRIPT}
  • Figures {POSTSCRIPT}

• Harmonic Balance Device Analysis of an LDMOS RF Power Amplifier with Parasitics and Matching Network (SISPAD '97 - Sept. 1997)
  -Rotella, Yu, Dutton

• Gridding Techniques for Level Set Method in Semiconductor Process and Device Simulation (SISPAD '97 - Sept. 1997)
  -Kan, Hsiau, Rao, Dutton
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• A Computationally-Stable Quasi-Empirical Compact Model for the Simulation of MOS Breakdown in ESD-Protection Circuit Design (SISPAD '97 - Sept. 1997)
  -Lim, Zhang, Yu, Beebe, Dutton
  • Text {POSTSCRIPT, PDF}

• Mixed-Technology CAD for Integrated Systems--a Confluence of Electrical and Mechanical Perspectives (Fourth USCCM - Aug. 1997)
  -Dutton, Kan
  • Text {POSTSCRIPT, PDF}

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1996

• The TCAD Road Ahead (IEDMS Conference - December 1996)
  -Dutton

• Distortion Analysis of GaAs MESFETs Based on Physical Model using PISCES-HB (IEDM '96 - Dec. 1996)
  -Sato-Iwanaga, Fujimoto, Masato, Ota, Inoue, Troyanovsky, Yu, Dutton
  • Text {POSTSCRIPT}

• Circuit Embedded Device Simulation for Heterogeneous Circuitry (ICCAD '96 - Nov. 1996)
  -Rotella, Dutton
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• Large Signal Analysis of RF/Microwave Devices with Parasitics Using Harmonic Balance Device Simulation (SASIMI '96 - Nov. 1996)
  -Troyanovsky, Rotella, Yu, Dutton, Sato-Iwanaga
  • Text {POSTSCRIPT, PDF}

• A New Practical Method to Include Recombination-Generation Process in Self-Consistent Monte Carlo Device Simulation (SISPAD '96 - Sept. 1996)
  -Jin, Kan, Dutton

• ESD Simulation to Find Correlation Between Junction Depth and Snapback Slope Using 0.35µm LDD MOSFETS (TECHCON '96 - Sept. 1996)
  -Zhang, Yu, Dutton, Beebe
  • Text {POSTSCRIPT}

• A TCAD Based "Golden Standard" for MOS Technology Scaling and Compact Model Development (TECHCON '96 - Sept. 1996)
  -Mujtaba, Kan, Pinto, Rafferty, Yu, Dutton

• Parasitic Characterization of Radio-Frequency (RF) Circuits Using Mixed-Mode Simulation (CICC '96 - May 1996)
  -Jang, Kan, So, Dutton, Johansson, Arnborg
  • Text {POSTSCRIPT}

• Challenges in Computational Prototyping of Deep Sub-Micron Integrated Circuit Technology (NASA Workshop, March 1996)
  -Dutton
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• Parallel Adaptive Finite Element Software for Semiconductor Device Simulation (ARPA Contract Final Report)
  -Dutton, Law, Pinsky, Aluru, Herndon
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• TCAD for Analog Circuit Applications: Virtual Devices and Instruments (ISSCC '96 - Feb. 1996)
  -Dutton, Troyanovsky, Yu, Kan, Wang, Chen, Arnborg
  • Text {POSTSCRIPT}

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1995

• Unification of Macroscopic Impact Ionization Models for Nonhomogeneous Fields (ISSDT '95 - Nov. 1995)
  -Kan, Dutton
  • Text {POSTSCRIPT}

• Relaxation-Based Harmonic Balance Technique for Semiconductor Device Simulation (ICCAD Conference - Nov. 1995)
  -Troyanovsky, Yu, So, Dutton
  • Text {POSTSCRIPT, PDF}

• Dynamic Trapping Model for Analysis of GaAs MESFETs and Quantum Well Lasers (ICSICT '95 - Oct. 1995, China)
  -Yu, Dutton, Harrison, Liu
  • Text {POSTSCRIPT}

• Physical Modeling of Surface and Heterojunction for Mesa-Structured HBTs (1995 GaAs IC Symposium - Oct. 1995)
  -Kan, Dutton
  • Text {POSTSCRIPT}

• An Accurate NMOS Mobility Model for 0.25µm MOSFETs (SISDEP '95 Conf. - Sept. 1995)
  -Mujtaba, Pinto, Boulin, Rafferty, Dutton
  • Text {POSTSCRIPT}

• Large Signal Frequency Domain Device Analysis Via the Harmonic Balance Technique (SISDEP '95 Conf. - Sept. 1995)
  -Troyanovsky, Yu, Dutton
  • Text {POSTSCRIPT}

• Advance in Numerical Methods for Convective Hydrodynamic Model of Semiconductor Devices (SISDEP '95 Conf. - Sept. 1995)
  -Aluru, Law, Dutton
  • Text {POSTSCRIPT}

• Design and Layout of a High ESD Performance NPN Structure for Submicron BiCMOS/Bipolar Circuits (IRPS Dallas, TX, Sept. 1995)
  -Chen, Zhang, Amerasekera, Vrotsos

• Hot Electron Transistors on Silicon Substrate (HESS) (1995 IEEE Cornell Conf. - Aug. 1995)
  -Kan, Jin, Dutton
  • Text {POSTSCRIPT}

• Layout-based 3D Solid Modeling for IC (VLSI TSA Conference - June 1995, Taipei, Taiwan)
  -Yu, Wang, Chen, Dutton, Watt
  • Text {POSTSCRIPT}

• FIESTA-HD: A Parallel Finite Element Program for Hydrodynamic Device Simulation (Parallel CFD '95, California Inst. of Technology - June 1995)
  -Aluru, Law, Raefsky, Dutton

• Accurate Modeling of Coulombic Scattering and its Impact on Scaled MOSFETs (1995 Symposium on VLSI Technology - June 1995)
  -Mujtaba, Takagi, Dutton
  • Text {POSTSCRIPT}

• Virtual Instruments for Development of High Performance Circuit Technologies (CICC '95 - May 1995)
  -Dutton, Yu, Rotella, Beebe, Troyanovsky, So
  • Text {POSTSCRIPT}

• Device Circuit Simulation for Heterogeneous Technology (SASIMI '95 - April 1995)
  -Yu, Rotella, Troyanovsky, Dutton
  • Text {POSTSCRIPT}

• Parallelizing a PDE Solver: Experiences with PISCES-MP (Aizu Int'l Symposium of Parallel A/A Syn - March 1995)
  -Herndon, Raefsky, Goossens, Dutton

• A Methodology for Parallelizing PDE Solvers: Applications to Semiconductor Device Simulation (SIAM '95 - Feb. 1995)
  -Herndon, Aluru, Raefsky, Goossens, Law, Dutton

• Methodology for Layout Design and Optimization of ESD Protection Transistors (Proc. 18th EOS/ESD Symposium, 1995, pp. 265-275)
  -Beebe

• Pisces 2ET with Applications Documentation
  -Yu, Chen, So, Beebe, Goossens, Rotella, Dutton
  • Text {POSTSCRIPT}

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1994

• A Self-Consistent Approach to Substrate Current Simulation in Submicron MOSFETs (EDMS '94 - July 1994)
  -So, Kan, Yu, Dutton

• Semi-Empirical Local NMOS Mobility Model for 2-D Device Simulation Incorporating Screened Minority Impurity Scattering (NUPAD V Conf. - June 1994)
  -Mujtaba, Scharfetter, Dutton
  • Text {POSTSCRIPT}

• Technology CAD: Computer Simulation (NTU Short Course - June 1994)
  -Dutton

• Dual Energy Transport Model for Advanced Device Simulations (IWCE '94 - May 1994)
  -Yu, So, Kan, Dutton

• An Alternative Method for Compact Model Construction and Parameter Extraction (IWCE '94 Poster, May 1994)
  -Kan, Dutton

• Integrated TCAD for OEIC Applications (OE/LASE '94, SPIE Workshop - Jan. 1994)
  -Dutton, Rotella, Sahul, So, Yu

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1993

• New Challenge in Device Design for Integrated Electronic Systems (Proc. Int'l Semi. Dev. Res. Symp. '93 - Dec. 1993)
  -Dutton, Yu

• Dual Energy Transport Model for Coupled Lattice and Carrier Systems (TECHCON '93 - Sept. 1993)
  -So, Chen, Yu, Dutton

• The Role of TCAD in Parasitic Analysis of ICs (Invited Paper, ESSDERC '93 - Sept. 1993)
  -Dutton

• Technology CAD at Stanford University: Physics, Algorithms, Software, and Applications (SISDEP '93 - Sept. 1993)
  -Dutton, Goossens

• Improvement of Initial Solution Projection in Solving General Semiconductor Equations Including Energy Transport (SISDEP - Sept. 1993)
  -So, Chen, Yu, Dutton

• Virtual Instruments--Concept and Implementation (SASIMI '93, 1993)
  -Yu, Dutton

• An Efficient Impact Ionization Model for Silicon Monte Carlo Simulation (1993 VPAD Digest, pp. 42-43 - May 1993)
  -Yao, Chen, Dutton, Venturi, Sangiorgi

• Algorithms and TCAD Software Using Parallel Computation (1993 VPAD Digest, pp. 10-12 - May 1993)
  -Dutton

• Robust Simulation of GaAs Devices Using Energy Transport Model (1993 VPAD Digest, pp. 32-33 - May 1993)
  -So, Chen, Yu, Dutton

• Space-time Galerkin/Least Squares Finite-Element Formulation for the Hydrodynamic Device Equations (1993 VPAD Digest, pp. 16-17 May 1993)
  -Aluru, Law, Pinsky, Raefsky, Goosens, Dutton

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1985

• PISCES-IIB Supplementary Report
  -Pinto, Rafferty, Yeager, Dutton
  • Text {PDF}

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1984

• PISCES-II: Poisson and Continuity Equation Solver
  -Pinto, Rafferty, Dutton
  • Text {PDF}

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