Challenges in Computational Prototyping of Deep Sub-Micron Integrated Circuit Technology*
Robert W. Dutton
Director of Research
Center for Integrated Systems
Stanford University
Abstract: The ongoing push to scale IC technology into the deep sub-micron regime poses many challenges in terms of creating atomic scale structures and in modeling them, both functionally and physically. This presentation will report on progress in creating and using advanced technology computer-aided design (TCAD) tools for computational prototyping of such advanced technologies including nano-devices. This work includes advances in: geometry-based physical specification, parallel computation of complex 2D-3D IC structures, the impact of object-oriented methods in software design and process modeling that bridges both continuum and atomic-level effects. Experiences in terms of consortia efforts in leveraging broader industrial involvement will also be considered.
Outline of Talk and Supporting Materials: The following set of attachments are intended to give a flavor of materials to be presented in the talk. Attachment 1 titled "Layout-Based 3D Solid Modeling of ICs" is the extended abstract of a talk presented at the International Symposium on VLSI Technology, Systems and Applications, held in Taiwan on May 31-June 2, 1995. It
describes some of the key software issues that have come out of collaborative "computational prototyping" of advanced SRAM structures. In the talk, I will present additional information about necessary supporting infrastructure that includes: layout information, solid geometry modeling tools, common information interchange and persistent data storage mechanisms.
Attachment 2 titled "Hierarchical Process Simulation for Nano-Electronics" is the extended abstract of a talk presented at the International Workshop on Computational Electronics, held in Phoenix on October 30-November 2, 1995.
While the focus of that talk was on the process and atomic-scale models needed for advanced electronics, the overall scope of the paper suggests classes of intrinsic devices and interconnect modeling issues that are important in the broader context of computational electronics. Also, this paper points out in greater detail some of the challenges in software engineering by means of examples growing out of an effort to develop
ALAMODE (A LAyered MOdel Development Environment). Finally, Attachment 3 titled
"Parallel Adaptive Finite Element Software for Semiconductor Device Simulation" represents a
broad-brush summary of results coming from a three-year ARPA funded project (1991-94) that
parallelized 2D and 3D device simulation codes using both the conventional drift-diffusion
formulation (i.e. PISCES) as well as based on a hydrodynamic (HD) formulation and using
Galerkin Least Squares Finite Element Methodology (GLS-FEM). In addition to some of the
algorithmic and HPC scaling issues presented, there is interesting information about the
interactions coming from "Industry-Networked TCAD" (reflected in the project title for the
follow-on contract to be discussed---SPRINT-CAD). In summary, the three attachments present a
very relevant set of topics and issues pertaining to this workshop and directly supportive of the
paper abstract. All three documents can be directly linked from the Web using the following
address: http://www-ee.stanford.edu/ee/tcad/pubs.html.
*Funded through ARPA/ITO Contract #DABT63-93-C-0053 and #DABT63-95-C-0090.