Impact of Process Variations on VLSI Interconnects, Device
and Circuit Performance
The on-chip inductive impact on signal integrity has been a problem for
designs in deep-submicron technologies. The inductive impact increases clock
skew, max-timing and noise levels of bus signals. In this work, circuit
macro-models are bench-marked against test chip measurements in a 90 nm
technology. Circuit simulations show that there is significant
inductive impact on signal max-timing delay (about 10% push-out vs.
RC delay) and noise levels (about 2x RC noise). In nanometer technologies,
process variations have become a concern. Results show that device and
interconnect process variations add about 3% to the RLC max-timing impact.
However, their impact on RLC signal noise is not appreciable. Finally,
inductive impact in 65 nm and 45 nm technologies is investigated, which
indicates that the inductance impact will not diminish as technology scales.
In addition, interconnect density and thickness variations due to the chemical
mechanical polishing (CMP) process in the nanometer technologies have caused
interconnect parasitic RC variations. These variations were studied using
test chips and process-variation-aware extraction techniques were proposed.
Papers are published at SISPAD'05, CICC'05, GLSVLSI'06, and the IEEE Electron Device Letters.
- "Measurement and simulation of interconnect inductance in 90 nm
and beyond," presented at SISPAD'05, Tokyo, Japan, Sept. 2005. Here are the
paper and
the slides.
- "Simulation and analysis of inductive impact on VLSI interconnects
in the presence of process variations," presented at CICC'05,
San Jose, Sept. 2005. Here are the
paper and
the slides.
- "Measurement and Characterization of Pattern Dependent Process
Variations of Interconnect Resistance, Capacitance and Inductance in
Nanometer Technologies," presented at GLSVLSI'06, Philadelphia, PA, April
2006. Here are the paper and the slides.
- "Simulation of Interconnect Inductive Impact in the Presence of Process Variations in 90 nm and Beyond," IEEE Electron Device Letters, Aug. 2006. Here is the paper .
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