On-Chip Inductance Modeling of VLSI Interconnects Including
Power/Ground Grids
Modeling of on-chip inductance is studied, which
captures 3-D geometry and process technology effects. The 3-D geometries are
automatically constructed based on layout information and technology
profiles. Analytical formulae suitable for design are used to estimate
inductance of test structures. S-parameter characterization up to
10 GHz shows good agreement with simulations and analytical modeling.
Consideration of substrate effects results in a reduction of wire
inductance for large wire spacing to ground lines.
Papers were presented
at 2000 IEEE International Solid-State Circuits Conference (ISSCC'00, Feb, 2000),
1999 IEEE International Electron Devices Meeting (IEDM'99, Dec. 1999),
The 10th Workshop on Synthesis and System Integration of Mixed Technologies
(SASIMI'01, Oct.,
2001) and other conferences.
- ISSCC'00 paper{pdf} and
slides{pdf}.
- IEDM'99 paper{pdf}.
- SASIMI'01 paper{pdf}.
- JSSC'02 paper{pdf}.
- GLSVLSI'03 paper{pdf}.
- A book chapter, "Interconnect parasitic extraction of resistance,
capacitance, and inductance" (Qi and Dutton), is published in the book
Interconnect Technology and Design for Gigascale Integration ,
(Edited by Davis and Meindl), Kluwer Academic Publishers (October 2003).
The book is available at Amazon.com.
- A short paper, "Full-chip inductive effects screening using simulation-based look-up table", (X. Qi et al) in Research Disclosure Journal ,
Kenneth Mason Publications Ltd, UK, May, 2004.
- ISQED'05 paper{pdf}.
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