Publications

Publications

Book and Book Chapter

Xiaoning Qi, "High Frequency Interconnect Characterization and Modeling - for VLSI On-chip Interconnects and RF Package Wire Bonds," ISBN: 978-3-639-13095-9, VDM Verlag, Germany, 2009. (The book is available at Amazon.com)
Xiaoning Qi and Robert W. Dutton, "Interconnect parasitic extraction of resistance, capacitance and inductance," in Interconnect Technology and Design for Gigascale Integration, edited by J. A. Davis and J. D. Meindl, Kluwer Academic Publishers, ISBN: 1-4020-7606-1, Boston, 2003. (The book is available at Amazon.com)

Refereed Journal Articles

W. Xu, G. Wang, J. Jiang, Xiaoning Qi, and F. Zhang, "A high-PSR transient-enhanced output-capacitorless CMOS low-droput regulator for SoC applications," International Journal of Electronics, pp. 1319-1332, Vol. 98, No. 10, London, UK, October, 2011.
Xiaoning Qi, S. C. Lo, A. Gyure, Y. Luo, M. Shahram, K. Singhal and D. B. MacMillen, "Efficient sub-threshold leakage current optimization and layout migration for 90nm and 65nm ASIC libraries," IEEE Circuits and Devices, Vol. 22, No. 5, pp. 39-47, Sep./Oct. 2006.
Xiaoning Qi, A. Gyure, Y. Luo, S. C. Lo, M. Shahram, and K. Singhal, "Simulation of interconnect inductive impact in the presence of process variations in 90 nm and beyond," IEEE Electron Device Letters, Vol. 27, No. 8, pp. 696-698, Aug. 2006.
B. Kleveland, Xiaoning Qi, L. Madden, T. Furusawa, R. Dutton, M. Horowitz and S. Wong, "High-frequency Characterization of on-chip digital interconnects," IEEE Journal of Solid-State Circuits, Vol. 37, No. 6, pp. 716-725, June 2002.
G. Wang, Xiaoning Qi, Z. Yu and R.W. Dutton, "Device level modeling of metal-insulator semiconductor interconnects," IEEE Transactions on Electron Devices, Vol. 48, No. 8, pp. 1672-1682, Aug., 2001.
Xiaoning Qi, C. Yue, T. Arnborg, H. Soh, H. Sakai, Z. Yu and R. Dutton, "A fast 3-D modeling approach to electrical parameters extraction of bonding wires for RF circuits," IEEE Transactions on Advanced Packaging, Vol. 23, No. 3, pp. 480-488, Aug. 2000.
Xiaoning Qi, Z. Feng and X. Yan, "Timing driven floorplanning," Acta Electronica Sinica, Vol. 23, No.2, pp. 103-105, Feb. 1995.
Xiaoning Qi, N. Zheng and X. Yan, "An algorithm of timing driven partitioning for MCMs," Microelectronics & Computer, Special Issue, pp. 30-33, Oct. 1995.
Xiaoning Qi, F. Zhou, Z. Feng, X. Yan and P. Zhu, "Timing driven floorplanning and cell generation," Microelectronics & Computer, Special Issue, pp. 37-39, Oct. 1995.
Z. Li, N. Zheng, Xiaoning Qi and X. Yan, "An algorithm of zero skew clock routing based on weighting selection," Microelectronics & Computer, Special Issue, pp. 47-49, Oct. 1995.
Xiaoning Qi, Z. Feng and X. Yan, "Timing driven floorplanning for general cells," IEE Electronics Letters, Vol.30, No.14, pp. 1112-1113, United Kingdom, July 1994.
Z. Feng, Xiaoning Qi and X. Yan, "Optimized physical routing for P/G nets in VLSI layout synthesis," Microelectronics & Computer, Vol.11, No.4, pp. 1-4, 1994. .
Xiaoning Qi, Z. Feng and X. Yan, "Optimizing method for cell delay in VLSI floorplanning," Journal of Hangzhou Institute of Electronics Engineering, Vol.14, No.2, pp. 1-5, 1994.
Z. Feng, Xiaoning Qi, and N. Zheng, "An automatic layout system for LSI chip design," Journal of Hangzhou Institute of Electronics Engineering, Vol. 14 No.1, pp. 7-13, 1994.
X. Yan, Xiaoning Qi, J. Lin, "A method of VLSI timing driven placement," Acta Electronica Sinica, Vol.21, No.2, pp. 28-33, Feb. 1993.
Xiaoning Qi and X. Yan, "An algorithm for timing driven iterative placement," in New Advances of CAD/CAM in China, Press of Zhejiang University, Hangzhou, China, 1991.
P. Zhu, Xiaoning Qi, F. Zhou, "The design of CMOS digital multiplier with concurrent structure," Acta Electronica Sinica, Vol. 18, No. 3, pp. 26-31, May 1990.

Refereed Conference Papers

S. Puligundla, K. Yong, W. Song, V. Kasturi, S. Ji and X. Qi,"Signal integrity consideration in implementing USB on-the-go for mobile designs," IEEE International Symposium on Electromagnetic Compatibility & Signal Integrity, Santa Clara, California, March, 2015.
Y. Sun, X. Qi and A.Z. Ramirez, "The 3D modeling and SI/PI co-sim analysis for mixed-referenced high speed GDDR5," 2012 8th International Caribbean Conference on Devices, Circuits, and Systems (ICCDCS), pp. 1-6, Playa del Carmen, March 14-17, 2012.
W. Xu, X Shi, G. Wang, J. Jiang, and X. Qi, "A CMOS LC-VCO with enhanced PSR based on common-mode replica compensation," 2010 International Conference on Computer Application and System Modeling, V8, pp. 174-177, Taiyuan, Oct, 2010.
X. Qi, J. Kim, L. Yang, R. Schmitt and C. Yuan,"Compact on-chip wire models for the clock distribution of high-speed I/O interfaces," IEEE 17th Conference on Electrical Performance of Electronic Packaging and Systems (EPEP), pp. 235-238, San Jose, October, 2008.
R. Vattikonda, Y. Luo, A. Gyure, Xiaoning Qi, S. Lo, M. Shahram, Y. Cao, K. Singhal, and D. Toffolon, "A new simulation method for NBTI analysis in SPICE environment," The 8th International Symposium on Quality Electronic Design (ISQED), San Jose, March 2007.
Xiaoning Qi, A. Gyure, Y. Luo, S. C. Lo, M. Shahram, and K. Singhal, "Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance in nanometer technologies," Proceedings of the 16th ACM/IEEE Great Lakes Symposium on VLSI, pp. 15-18, Philadelphia, PA, April 2006.
Xiaoning Qi, S.C. Lo, Y. Luo, A. Gyure, M. Shahram, and K. Singhal, "Simulation and analysis of inductive impact on VLSI interconnects in the presence of process variations," Proceedings of IEEE 2005 Custom Integrated Circuits Conference (CICC), pp. 309-312, San Jose, CA, Sep. 2005.
Xiaoning Qi, A. Gyure, Y. Luo, S.C. Lo, M. Shahram, and K. Singhal, "Measurement and simulation of interconnect inductance in 90nm and beyond," Proceedings of IEEE 2005 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 111-114, Tokyo, Japan, Sep. 2005.
N. Srivastava, Xiaoning Qi and K. Banerjee, "Impact of on-chip inductance on power distribution network design for nanometer scale integrated circuits," Proceedings of the 2005 International Symposium on Quality Electronic Design, pp. 346-351, San Jose, March, 2005.
Xiaoning Qi, G. Leonhardt, D. Flees, X. Yang, S. Kim, S. Mueller, H. Mau and L. Pileggi, "A fast simulation approach for inductive effects of VLSI interconnects," Proceedings of the 13th ACM Great Lakes Symposium on VLSI, pp. 108-111, Washington D.C., April, 2003.
G. Wang, Xiaoning Qi, Z. Yu and R. Dutton, "Accurate model of metal-insulator-semiconductor interconnects," Proceedings of the 3rd International Symposium on Quality Electronic Design, pp. 48-52, March, 2002.
Xiaoning Qi, B. Kleveland, G. Wang, Z. Yu, S. Wong, R.W. Dutton and T. Furusawa, "High frequency characterization and modeling of VLSI on-chip interconnects," Proceedings of the Tenth Workshop on Synthesis and System Integration of Mixed Technologies, pp. 370-376, Japan, Oct. 2001.
Xiaoning Qi, G. Wang, Z. Yu, R. Dutton, T. Young, and N. Chang, "On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulations," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pp. 487-490, May 2000.
Xiaoning Qi, B. Kleveland, Z. Yu, S. Wong, R. Dutton and T. Young, "On-chip inductance modeling of VLSI interconnects," IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 172-173, Feb. 2000.
O. Tornblad, J. Jang, Xiaoning Qi, T. Arnborg, Q. Chen, Z. Yu and R. Dutton, "Compact electrothermal modeling of RF power LDMOS," Proceedings of the Workshop on Synthesis and System Integration of Mixed Technologies, pp. 146, Japan, April 2000.
G. Wang, Xiaoning Qi, Z. Yu, R. Dutton and C. Rafferty, "Large signal analysis of on-chip interconnects using transport based approach," Proceedings of The Fifth International Symposium on Antennas, Propagation, and EM Theory, Aug. 2000.
B. Kleveland, Xiaoning Qi, L. Madden, R. Dutton and S. Wong, "Line inductance extraction and modeling in a real chip with power grid," Technical Digest of IEEE International Electron Devices Meeting (IEDM), pp. 901-904, Dec. 1999.
Xiaoning Qi, P. Yue, T. Arnborg, T. Soh, Z. Yu, R. Dutton and H. Sakai, "A fast 3D modeling approach and parasitic extraction of bonding wires for RF circuits," Technical Digest of IEEE International Electron Devices Meetings (IEDM), pp. 299-302, Dec. 1998.
Xiaoning Qi, S. Shen, Z. Hsiau, Z. Yu and R. Dutton, "Layout-based 3-D solid modeling of IC structures and interconnects including electrical parameter extraction," Proceedings of IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 61-64, Sept. 1998.
Xiaoning Qi, Z. Feng and X. Yan, "Timing driven floorplanning with pin assignment," Proceedings of the First International Conference on ASIC, Beijing, pp. 213-216, Oct. 1994.
Xiaoning Qi, Z. Feng and X. Yan, "An algorithm of timing driven floorplanning for VLSI layout design," Proceedings of the 4th International Conference on Computer-aided Drafting, Design and Manufacturing Technology, Beijing, Aug. 1994.
Z. Feng, Xiaoning Qi and X. Yan, "Physical routing for channels with P/G nets optimization in general cell layout," Proceeding of the 4th International Conference on Computer-aided Drafting, Design and Manufacturing Technology, Beijing, Aug. 1994.
Z. Feng, N. Zheng, Xiaoning Qi, and X. Yan, "HEART: a placement and routing system for VLSI," Proceedings of 4th National Design Automation Conference, Ningbo, 1993.

Invited Talks

Xiaoning Qi, "Smart technologies and smart life," Zhejiang University, Hangzhou, Oct. 2014.
Xiaoning Qi, "Moden computing and EDA needs," Huada Design Systems, Beijing, Oct. 2012.
Xiaoning Qi, "Cloud computing," Zhejiang University, Hangzhou, Oct. 2011.
Xiaoning Qi, "Power integrity design in high speed I/O chips," Hangzhou Dianzi University, Hangzhou, Nov. 2009.
Xiaoning Qi, "Design for IC manufacturing variabilities," Hangzhou Dianzi University, Hangzhou, Oct. 2008.
Xiaoning Qi, W. Liu, and D. MacMillen, "Compact modeling for IC simulation: the industrial needs and solutions," The First Asian Nano-Device Modeling Initiative Workshop, Hangzhou, China, Oct. 2006.
Xiaoning Qi, G. Wang, and M. Shahram, "Modeling and full-chip screening for inductive impact on VLSI interconnects," Proceedings of the 2006 China- Ireland International Conference on Information and Communications Technologies, Hangzhou, Oct. 2006.
Xiaoning Qi, "Modeling and design of interconnects, devices and packaging for advanced SoCs," The ECE Department, University of Illinois, Urbana-Champaign, April 2006.
Xiaoning Qi, "Modeling the on-chip VLSI interconnects," The Center for Computer-Aided Design, Hangzhou Institute of Electronics Engineering, Hangzhou, China, Sep. 2005.
Xiaoning Qi, "Modeling the on-chip VLSI interconnects," The Institute of Microelectronics, Wuhan University, Wuhan, China, Sep. 2005.
Xiaoning Qi, "Modeling and simulation for high frequency effects of VLSI interconnects," The ECE Department, University of California, Santa Barbara, Oct. 15, 2004.

Other Journal/Conference Papers and Technical Reports

X. Qi and R. Mittal, "A Top-down methodology for clocking moden mobile platfroms," Intel SI/PI Joint Seminar, Jan. 2015.
H. Wang, X. Qi, K. Tran, "MIPI-DSI DPHY POR Rx SI validation methodology enhancement and automation," Intel SI/PI Joint Seminar, Jan. 2014.
X. Qi, S. Ji, G. Gerosa, H. Wang and B. Patel, "Novel power delivery design metrics with signal integrity impacts," Intel Design and Test Technology Conference (DTTC), Aug. 2012.
R. Schmitt, X. Qi and H. Lan, "Prediction and measurement of supply noise induced jitter in high-speed I/O interfaces," Rambus, Inc., Feb. 2008.
X. Qi, "How to extract Verilog-A macro model parameters using Aurora-HSPICE," Synopsys, Inc., Sep. 2006.
X. Qi, "Sub-threshold leakage current optimization and layout migration for an industry 65 nm library," Synopsys, Inc., July 2006.
X. Qi, "A case study: Verilog-A modeling and simulation of Op-Amps," Synopsys, Inc., July 2006.
X. Qi and G. Konstandinidis, "Modeling and simulation of VLSI interconnects for gigascale integration," SUN Engineering Conference, Feb. 2005.
X. Qi, D. Flees and G. Leonhardt, "Full-chip inductive effects screening using simulation-based look-up table," Research Disclosure Journal, Kenneth Mason Publications Ltd, United Kingdom, May 2004.
X. Qi and G. Konstadinidis, "Dynamic noise simulation for on-chip power ground grids with package models," Power Summit 2004, Sun Microsystems, Inc., 2004.
X. Qi and G. Konstadinidis, "Inductive impact on timing and noise for sub-130 nm technologies," Sun Microsystems, Inc. 2003.
X. Qi, D. Flees, and G. Leonhardt, "Time-domain inductive impacts modeling for VLSI on-chip interconnects," Sun Microsystems, Inc., 2001.
X. Qi, "On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulations," Center for Integrated Systems (CIS), Stanford University, 1999.
X. Qi, "A simple circuit model of bonding wires for RF circuits," CIS, Stanford University, Aug. 1998.
X. Qi, "Package capacitance modeling of an IC chip," CIS, Stanford University, Sept. 1997.
X. Qi, "Network reduction for interconnects in VLSI circuits," CIS, Stanford University, July 1997.

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