Atsushi Kawamoto Ph.D. Candidate Department of Electrical Engineering Stanford University
	Office	CISX 300, MS 4075 Stanford, CA 94309
	Contact Information	Phone: (650) 725-6078 Fax: (650) 725-7731 Email: kawamoto@stanford.edu URL:  http://www-tcad.stanford.edu/~kawamoto
	Home Education Honors Research	Thanks for visiting my home page!  I am a third-year E.E. Ph.D. candidate in Prof. Bob Dutton's group at Stanford University. My research focuses on the use of first principles computational methods to address challenges for aggressively scaled CMOS technology.  Currently I am investigating alternative high-k dielectric materials as possible replacements for thermally grown SiO2 in sub-100nm CMOS. Education Ph.D. Electrical Engineering Stanford University (expected 9/2001) M.S. Electrical Engineering Stanford University (1998) B.S. Electrical Engineering Stanford University (1997) Classes Projects Honors National Science Foundation Graduate Research Fellowship (1998-2001) Thomas and Sarah Kailath Fellowship (1998) Frederick E. Terman Award (1997) Elected to Phi Beta Kappa and Tau Beta Pi (1996) Research Alternative high-k gate dielectric materials My thesis works focuses on the use of first principles methods based on density functional theory (DFT) to investigate alternative high-k gate dielectrics.  By using a first principles approach to directly investigate atomic scale phenomena, I am hoping to provide useful insight into the on-going, heavily experimental search for the replacement gate dielectric. I am co-advised by Prof. Bob Dutton and Dr. Peter Griffin.  I also work closely with Prof. KJ Cho and his group. Experiences Publications Presentations References to the literature. This page last modified on 06/14/00 07:22 PM.