Some projects I've worked on at Stanford

Home Semiconductor device and process physics First principles computation VLSI circuits and systems

Semiconductor device and process physics EE410 Integrated Circuit Fabrication Laboratory: Complete 1.5um CMOS process flow Fabricated and tested a complete 1.5um CMOS process flow in Center for Integrated Systems (CIS) facility. in Center for Integrated Systems CIS) facility. Modeled entire process flow using TSUPREM 4 and MEDICI. EE391 Directed Research: Device simulation of suppression of short-channel effects with Indium doping Investigated possible use of Indium doping to suppress short-channel effects in scaled CMOS using MEDICI. First principles computation ChemE444A Quantum Simulations of Molecules and Materials: Quantum chemical study of transition metal oxide clusters Investigated relation between polarizabilities of ZrO4 and HfO4 clusters and macroscopic dielectric constants of high-k metal oxide films via the Clausius-Mossotti relation using Gaussian98, a quantum chemistry program. ME249B Quantum Simulations – Materials Micro Mechanics: Ab-initio investigation of stress-induced bandgap narrowing in Si Determined deformation potentials relating stress to changes in electronic structure of Si using first principles total energy pseudopotential methods. VLSI circuits and systems EE271 Introduction to VLSI Design: Design of 8-bit microprocessor datapath Designed, simulated, and tested a datapath for an 8-bit microprocessor, including Verilog functional specification, Magic layout, and IRSIM verification and timing analysis. EE214 Analog Integrated Circuit Design: Design of 5W audio power amplifier Designed, simulated, and tested a high output bipolar power amplifier with low distortion using HSPICE, including extensive calculations to estimate achievable gain, output current, frequency response, and optimal transistor sizing. EE183 Advanced Logic Design Laboratory: Design of 12-bit pipelined RISC microprocessor with vector processing unit Designed, implemented, and tested a 12-bit pipelined RISC processor using Workview schematic capture and Xilinx FPGA design environment. This page last modified on 06/06/00 03:11 PM.