January 1 - March 31, 1995


Stanford University




Robert W. Dutton, dutton@gloworm.Stanford.EDU, (650) 723-4138
Kincho H. Law, law@cive.Stanford.EDU, (650) 725-3154
Krishna Saraswat, saraswat@ee.Stanford.EDU, (650) 725-3610
Peter Pinsky, pinsky@ce.Stanford.EDU


Edwin C. Kan, kan@gloworm.Stanford.EDU, (415) 723-9796


"SPRINT-CAD"---Industry-Networked TCAD using Shared Parallel Computers


The URL for Stanford TCAD projects is: http://www-tcad.stanford.edu


First-time capabilities to bridge solid modeling, FEM-based parallel computation of fabrication processes and electrical analysis of the resulting IC structures will be developed. Models needed to represent diffusion, etching, deposition, oxidation and stress analysis resulting from a sequence of process steps necessary in the creation of electrical devices will be developed. This effort will provide a radically new HPC framework for technology-based 3D process/device modeling as well as realistic benchmarks to test HPC architectures and software.


We will build, integrate and test TCAD modules based on an object-oriented approach that both develops and uses information models in support of CFI-based standards. The modules and software engineering methodology will be designed specifically to exploit parallel computers and library components. The 3D process simulation modules will utilize HPC platforms and provide new functional capabilities for "computational prototyping" of the following key technology fabrication steps:
  1. deposition/etching module---of special interest are CVD and plasma assisted processes that result in high aspect ratio structures such as trenches and filling/planarization of structures for metal interconnects. Algorithmic work focuses on geometric manipulations and surface evolution.
  2. thermal/stress analysis module---that can solve nonlinear constitutive models for key process steps involving growth of dielectric layers and impurity redistribution as well as the resulting stress fields. Advanced formulations for finite elements are being developed that support: parallel computation, adaptive gridding and domain decomposition.


The solid geometry modeling VIP-3D has been utilized to prototype a commercial wireless communication BJT. This is a first-time demonstration of the ability to go directly from IC process and mask specifications to extraction of RF distortion. The details are listed in the section of significant events below. The CAMINO 3D gridding has been investigated for realistic device and process modeling, with static mesh on 3D device structure and dynamic mesh on 3D diffusion and oxidation processes.

The dial-an-operator finite element analysis program has been named as a-la-mode (A Layered Approach MODEling) since the user has layered access to the built-in physical model and parameters, physical formulations, numerical schemes, geometry and field manipulation, etc. to maximize both software configurability and user friendliness. The object model of TCL (tool control language) has been implemented and the user can now describe the physical definition, numerical schemes and various input and control in the TCL extension language. We have demonstrated that a reactive-diffusive model for Phosphorous diffusion in 2D containing five interacting specifies (i.e., five coupled PDEs) can be completely described in a simple TCL script. The results have been benchmarked and compared favorably with the 1D PEPPER diffusion simulation tool. The code has been ported to the ALPHA machine and is currently used by several graduate students and research staffs to study the transient-enhanced-diffusion (TED) effect. One of the main authors (D. Yergeau) will work as an intern in Intel this summer, where a-la-mode will be applied to realistic processes and a set of diffusion coefficients for TED will be calibrated.

The new finite-deformation oxidation model has been originally tested in the the FEAP (finite element analysis program) environment. However, to reduce future duplicated efforts in integration with the geometry/field server and the parallelized linear solver, the interface of element calculation to FEAP is carefully analyzed and encapsulated, so that the basic element functions for this new oxidation model can become an operator-like description in the a-la-mode code.

The 3D etch/depo simulation using the physical models in SPEEDIE is under way. Presently we chose to wrap the SAMPLE-3D (Berkeley photo-lithography tool) by the minimal SWR specification and used it as a surface mesh field server. To prevent undercut in thin metal interconnect lines, more careful etch time control is necessary. However, this produces stringer problems on crossover. To model this phenomenon accurately, physical etching models in SPEEDIE will be extended to 3D. The interface to the wrapped SAMPLE-3D code is completed and various physical etch models are under investigation.




Documentation of the proposed minimal SWR specification has been prepared and discussed in detail with industrial partners including: IBM, ATT and Intel. In addition a proposal, with industrial and university partnerships, in response to BAA 95-18 was submitted as a "white paper" to ARPA. The objective of this proposal is to directly use and integrate the SWR server-based architecture into a computational prototyping environment that uses not only the SPRINT-CAD modules but also industrial TCAD tools from IBM and ATT. The response of the industrial collaborators, including Intel as a potential system user, has been highly enthusiastic. If successful in the final selection process, the proposed efforts can realize a heterogenous TCAD environment that would effectively transition both the SPRINT-CAD results as well as other industrial TCAD modules into broader availability and use within the microsystems community.

Ongoing development of the object-oriented PDE solver continues to create enthusiasm within the research and industrial communities. Intel has offered to be a "beta" test site this summer and one of the key developers of the Dial-an-Operator module will be directly involved with the implementation and testing at Intel. Within the SUPREM project at Stanford, supported through SRC, the Dial-an-Operator module will be tested internally as a replacement for the present diffusion module within SUPREM 4GS. This application based testing of the new object-oriented module also provides the basis for creating completely new applications, for example in support of computational prototyping of 21st century semiconductor devices (under separate ARPA support).



Researchers at Stanford have demonstrated for the first time the ability to go directly from IC device specification to electrical extraction of distortion in radio frequency (RF) circuits based on computational prototyping. Using IC layout-based specification of a complex RF bipolar power transistor, including both 3D and 2D computational models of devices, a new harmonic balance (HB) simulator directly supports the analysis and extraction of exactly which regions in the device contribute to harmonic and IM distortion. This new computational approach now allows the circuit designer and the IC technologist to communicate directly and unambiguously about the trade-offs being made in development of new structures for RF and other wireless applications. As an example, the Stanford team demonstrated the extraction of distortion for a 1.5 GHz bipolar cellular phone application. The IM tones can now directly be correlated with internal device effects such as collector and base doping parameters, thereby setting the stage for optimizations that will improve overall system performance.

Edwin C. Kan
201 AEL, Stanford University, Stanford, CA 94305
Office: (415)723-9796
Fax: (415)725-7731

Date prepared: 4/27/95