National Center for Computational Electronics

Introduction

1. Develop new physical models through collaborations among NCCE members
2. Develop computer tools and other means of technology transfer that supports the broad user base for computational electronics
3. Develop curricula and teaching methods that support the infrastructure of computational electronics and
4. Provide educational materials and organize meetings to enhance information exchange and transfer of knowledge

1. Physical Models - More than a year ago we began several collaborations in the area of transport modeling under auspices of NCCE. Specifically, the modeling and calibration of non-thermal transport in MOS devices has been a major focus. The following are the major areas of activity over the past year:
   1. further development of the energy transport or ET model
   2. calibration of full-band MC impact ionization results with simplified MC and HD formulations and
   3. calibration of physical parameters being used in a variety of MC codes throughout the world.
   The development of the ET model has been based primarily on the joint work of Stanford and Illinois with collaborations of: Dr. Mark Pinto of AT&T, Prof. Enrico Sangiorgi of University of Bologna and Dr. Edwin Kan of Dawn Technology (one of the three major TCAD vendors). In addition there have been technical discussions and exchanges with other academic and industrial groups as well as major TCAD vendors (Technology Modeling Associates and Silvaco Data Systems). Results of this work include both a number of papers and publications [1][8][10]11][12][13] and implementation of the ET model in a new version of the well-known Stanford PISCES code for 2D device analysis.

   The efforts to develop improved impact ionization modeling has to date primarily used the full-band MC results of Dr. Jeff Bude, developed while he was at Illinois, to extract simplified model coefficients for the BEBOP MC code developed by Prof. Sangiorgi and co-workes at University of Bologna. The results were presented this May at VPAD [13] and we have ongoing collaboration with Prof. Young June Park from Seoul National University as well as several industrial groups both in the US and internationally.

   Just prior to the May, 1992 workshop at NCCE, Dr. Jack Higman of Motorola suggested a "round robin" calibration effort to quantify and compare differences in MC results based on differences in physical model formulations and coefficients. At that NCCE meeting the preliminary results were presented and contributors were encouraged to further refine there results for a joint publication. Late this spring we sent out a final draft of the paper that will contain these "benchmarks" and we expect to have the paper published late this year or early in 1994. This effort is the first attempt we are aware of to do such a broad comparison and should be of major benefit to those in the field in establishing general guidelines for useful parameters and typical results for comparison.

2. Computer Tools and Technology Transfer - A majority of the Stanford development of TCAD tools is supported either through SRC or DoD (specifically ARO and ARPA). The SRC has focused almost exclusively on silicon-based technology and 2D tools such as SUPREM(process analysis) and PISCES (device simulation). The work in MC analysis using BEBOP from University of Bologna in connection with PISCES has come through industrial support and in part through the NCCE collaborations as discussed above. The DoD-based activities have tended to emphasize GaAs and other compound material systems including heterojunction devices. In the area of 3D device analysis we have focused our efforts on high-performance computing (HPC) using parallel computers and all support for these efforts has come through ARPA.

   In the context of the goals of NCCE we have been quite active in developing standards for tool integration and in interacting with industrial users of TCAD tools to understand the limitations from the industrial perspective. There have been several publications in the areas of tool integration [2][3][4][5][6][7][9].

   Each year in August Stanford holds an annual review of the status of both our internal research projects in tools and also to provide an environment for industrial, academic and vendor interactions. The August 1992 meeting emphasized the framework aspects of TCAD tool integration while this year's meeting discusses not only progress in tools but for the first time provides both sessions and exhibition time for TCAD vendor contributions. This year's meeting has been broadly publicized in the "TCAD Journal" sent by e-mail with Prof. Mark Law at the University of Florida as the editor. Coordination with bay area TCAD vendors and the Prof. Neureuther's group at University of California, Berkeley make this a major event that will provide those interested in TCAD a very exciting exposure.

3. Curricula and Teaching Methods - The area of computational electronics requires new developments in both curricula and teaching methods. Over a period of nearly ten years Stanford has taught a graduate course which uses both SUPREM and device analysis programs such as PISCES (and SEDAN an older 1D program). Over the past year Prof. Zhiping Yu (Tsinghua University) and Prof. Dutton (Stanford University) have completed a book titled "Technology CAD--Computer Simulation of IC Processes and Devices" that was published by Kluwer in August, 1993. At the Stanford August meeting a one-day "Introduction to TCAD" course was offered where both Profs. Dutton and Yu along with other key staff members provided both lectures and hands-on with the TCAD tools.

4. Other Organization and Infrastructure Issues - There has been a long and successful history of NCCE-organized events, particularly in the Chicago area. Over the past two years we have expanded the annual events to include the August meetings held at Stanford as well as affliated meetings such as the 1993 International Workshop on Computational Electronics to be held in Leeds, England this August as well. There are several major TCAD conferences--NUPAD (US), VPAD (Asia), SISDEP (Europe)--that provide key opportunities for interactions with NCCE. In fact, the May 1992 NCCE workshop was scheduled to make it possible for NUPAD conference attendees coming from abroad to attend both meetings in one trip. There are several further developments in the area of TCAD that deserve growing attention and support in connection with NCCE. Specifically, under support from SIA and with technical backing from both SRC and SEMATECH, a "Semiconductor Technology Roadmap" has been developed and published. This document has many specific recommendations in the TCAD area that interact with the mission of NCCE and we intend to both make recommendations and coordinate our planning in light of that document. In a similar spirit, under support from the TCAD Technical Subcommittee of the CAD Framework Iniative (CFI) there is ongoing efforts to develop information models for both a "Semiconductor Wafer Representation" (SWR) and "Semiconductor Process Representation" (SPR) that will provide needed means to integrate diverse TCAD tools as well as serve as a developer's framework for next generation TCAD tools. We plan to coordinate NCCE efforts with CFI meetings (as has been done in the past) and provide opportunities for both a dialog and joint meeting whenever possible.

Summary

• Completion of the ET model and it's prototype implementation both in Stanford's PISCES code as well as those of TCAD vendors
• Preparation of a publication that "benchmarks" various models and coefficients used in several dozen MC codes world-wide
• Two major events this August--Stanford's annual meeting and a Computational Electronics Workshop in Leeds, England--that provided both research and educational components related to the NCCE mission
• Publication of a book on TCAD that provides the basis for both graduate education in TCAD as well as industrial education through short-courses such as the Stanford August meeting .
• Ongoing coordination with both CFI and SIA activities

References

[1] D. Chen, E. C. Kan, U. Ravaioli, C. Shu and R. W. Dutton, ``An Improved Energy Transport Model for Hot-electron Device Simulation, '' @i(IEEE Elec. Dev. Lett.), vol. 13, no. 1, pp. 26-28, Jan. 1992.

[2] G. Chin and R. W. Dutton, ``A Tool Towards Integration of IC Process, Device, and Circuit simulation,'' @i(IEEE J. Solid-State Circuits), Vol. 27, No. 3, pp. 265-273, Mar. 1992.

[3] E. Scheckler, A. Wong, R. Wang, G. Chin, R. Dutton, ``A Utility-Based Integration System for Process Simulation,'' @i(IEEE Trans. CAD), Vol. 11, No. 7, pp. 911-920, June, 1992.

[4] R. Goossens, and R. W. Dutton, ``Device-CAD in the 1990's'', @i(IEEE Circuits and Devices Magazine), pp. 18-26, July 1992.

[5] R. Goossens, S. Beebe, Z. Yu, R. W. Dutton, ``An Automatic Biasing Scheme for Tracing Arbitrarily Shaped I-V Curves,'' Submitted to IEEE Transactions on CAD.

[6] R. W. Dutton, R. J.G. Goossens, ``Technology CAD at Stanford University, Physics, Algorithms, Software, and Applications,'' Edited by S. Selberherr, Submitted in May 1993.

Papers Presented

[7] Z. Yu, H. Wang, and R.W. Dutton, ``A Modularized, Mixed IC Device/Circuit Simulation System,'' @i( Proceedings SASIMI) '92, pp. 444-448, Kobe, Japan, April 1992.

[8] E. C. Edwin, D. Chen, U. Ravaioli and R. W. Dutton, ``Numerical Characterization of a New Energy Transport Model'', @i(International Workshop on Computational Electronics), U. Illinois, Urbana-Champaign, IL, May, 1992

[9] K. Wu, L. So, Z. Yu, R.W. Dutton, and J. Faricelli, ``Extraction of charge partitioning in multi-terminal devices with ac analysis approach,'' @i(International Workshop on Computational Electronics), U. Illinois, Urbana-Champaign, IL, May, 1992

[10] D. Chen, E. Sangiorgi, M. R. Pinto, E. C. Kan, U. Ravaioli and R. Dutton, ``Analysis of Spurious Velocity Overshoot in Hydrodynamic Simulations of Ballistic Diodes, '' NUPAD IV (Numerical Process and Device Modeling Workshop) Digest, pp. 109-114, Seattle, May 31--June 1, 1992.

[11] S. Sugino, D. Chen, N. Takakura and R. Dutton, ``Analysis of Writing and Erasing procedures of Flotox EEPROM Using the New Charge Balance Condition (CBC) Model, '' NUPAD IV (Numerical Process and Device Modeling Workshop) Digest, pp. 65-69, Seattle, May 31--June 1, 1992.

[12] L. So, D. Chen, Z. Yu, and R. W. Dutton, ``Robust Simulation of GaAs Devices Using Energy Transport Model,'' 1993 International Workshop on VLSI Process and Device Modeling (1993 VPAD) Digest, pp. 32-33, Nara Japan, May 14-15, 1993.

[13] C.-S. Yao, D. Chen, R. W. Dutton, F. Venturi, E. Sangiorgi, ``An Efficient Impact Ionization Model for Silicon Monte Carlo Simulation,'' 1993 International Workshop on VLSI Process and Device Modeling (1993 VPAD) Digest, pp. 42-43, Nara Japan, May 14-15, 1993.