TECHNICAL PROGRAM
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TECHNICAL PROGRAM
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The 1997 International Conference on simulation of Semiconductor Processes and Devices (SISPAD '97) will be held on September 8-10, 1997 at Boston Marriott Cambridge, Cambridge, Masachussetts.
Program for: Tuesday, September 9, 1997, Poster Session Wednesday, September 10, 1997REGISTRATION:
Sunday, September 7, 5:00 - 7:00pm
Monday, September 8, 7:30am - 2:00pm
| INVITED TALKS | |
| 8:30 - 9:15 | "Progress in Predicting Transient Diffusion" Conor Rafferty, Lucent Technologies |
| 9:15 - 10:00 | "Historical Perspective and Recent Development of Hot-Carrier
Generation Modeling for Device Analysis" Enrico Sangiorgi, University of Udine
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| Break (30 minutes) | |
| 10:30 - 11:15 | "Recent Advances in Krylov-Subspace Solvers
for Linear Systems and Applications in Device Simulation" Roland Freund, Bell Laboratories |
| 11:15 - 12:00 | "Application of TCAD to Designing Advanced DRAM and Logic Devices" K. Fukuda and Kenji Nishi, Oki Electric Industry Co., Ltd. |
| Lunch Break | |
| Session 1: Design of MOS Devices | |
| 1:30 - 1:55 | "Asymmetry in Effective-Channel Length of n- and p-MOSFETs", R. Logan, Y. Taur and E. Crabbe, IBM Semiconductor R&D Center, Hopewell Junction, NY |
| 1:55 - 2:20 | "VLSI Performance Metric Based on Minimum TCAD Simulations", G. Schrom, V. De* and S. Selberherr, TU Vienna, Vienna, Austria and *Intel Corp., Hilsboro, OR |
| 2:20 - 2:45 | "Layout Optimization of ESD Protection TFO-NMOS by Two-dimensional Device Simulation", D. Yim, H. Kim, D.Song, J. Baek, LG Semicon Co., Ltd., Seoul, Korea |
| Break (30 minutes) | |
| 3:15 - 3:40 | "Tilt Angle Effect on Optimizing HALO PMOS Performance", J. G. Su, S. C. Wong, C. T. Huang, C. C. Cheng, C. C. Wang*, S. Huang-Lu, and B. Y. Tsai*, Feng-Chia University, Taichung, Taiwan and *ERSO, Hsin-Chu, Taiwan |
| 3:40 - 4:05 | "Analysis of Channel-Width Effects in 0.3um Ultra-Thin SOI NMOSFETs", C.-H. Choi, S.-H. Lee, Y.-K. Park and J.-T. Kong, Samsung Electronics, Kyungki-Do, Korea |
| 4:05 - 4:30 | "A Characterization Tool for Current Degradation Effects of Abnormally Structured MOS Transistors" J.-K. Park, C.-H. Choi, Y.-K. Park, C.-S. Lee, J.-T. Kong, M.-H. Kim, T.-S. Kim and S.-H. Lee, Samsung Electronics, Kyungki-Do, Korea |
| 4:30 - 4:55 | "An Experimental Methodology for the Estimation of Spatially Correlated Parametric Yield in Thin Film Devices" E. T. Carlen and C. H. Mastrangelo, University of Michigan, Ann Arbor, MI
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| Session 2: Thin Films | |
| 1:30 - 1:55 | "Modeling Stress Effects on Thin Oxides Growth Kinetics", S.-F. Huang, P. B. Griffin, J. D. Plummer and P. Rissman*, Stanford University, Stanford, CA and *Hewlett-Packard, Palo Alto, CA |
| 1:55 - 2:20 | "Mechanical Stress Modeling for Silicon Fabrication Processes", H. A. Rueda and M. E. Law, University of Florida, Gainesville, FL |
| 2:20 - 2:45 | "Photoresist Process Optimization for Defects Using a Rigorous Topography Simulator", L. Milor, J. Orth, D. Steele, K. Phan, X. Li*, A. J. Strojwas*, Y.-T. Lin, Advanced Micro Devices, Sunnyvale, CA and *Carnegie-Mellon University, Pittsburgh, PA
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| Break (30 minutes) | |
| 3:15 - 3:40 | "Three-Dimensional Profile Evolution under Low Sticking Coefficient" D. Adalsteinsson and J.A. Sethian*, Lawrence Berkeley National Laboratory, and *University of California, Berkeley, CA |
| 3:40 - 4:05 | "A Method for Die-Scale Simulation of CMP Planarization" T.-L. Tung, Intel Corp., Santa Clara, CA |
| 4:05 - 4:30 | "CMP Profile Simulation Using an Elastic Model Based on Nonlinear
Contact Analysis" Y.-H. Kim, T.-K. Kim, H.-J. Lee, J.-T. Kong, and S.-H. Lee, Samsung Electronics, Kyungki-Do, Korea
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| 6:00 - 10:00pm | Dinner at the New England Aquarium
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