Other Projects
Network Reduction for Interconnects in VLSI Circuits:
Use transmission line theory to model and reduce the interconnect network;
Evaluate the effects of inductance, capacitance and resistance of interconnects in VLSI circuits. A new reduction algorithm was invented. Results were
presented in an internal research report.
Packaging Parasitics Modeling of IC Chips: Use Fastcap from
MIT, Raphael from TMA/Synopsys to model 2-D and 3-D
packaging parasitics
for IC chips, interconnect elements and device parasitics. A Matsushita
power device/chip's parasitics were analyzed in detailed. Results were
presented in an internal research report.
Physical Design for VLSI circuits: VLSI Timing driven placement and
routing were extensively studied and papers were published in international journals and conferences.
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