Compact Wire Models and Power Integrity for High-Speed I/O Interfaces
Efficient on-chip wire models are proposed for the low power and multi-gigahertz
clock distribution of high-speed I/O interfaces. As a result,
simulation can accurately model
multiple current returns and proximity effect at high frequencies. The model is
validated with measured S-parameters up to 20 GHz using a 90 nm test chip. The
effective loop inductance is shown to have 2x frequency variations which impacts
directly on the peak frequency of an LC resonance clock distribution.
A paper was published at IEEE Conference on Electrical Performance of
Electronic Packaging and Systems (EPEP Paper , October, 2008)
A system approach for analyzing supply noise induced timing jitter in high-speed
I/O interfaces is proposed. The method combines frequency-dependent supply noise
jitter sensitivity profile with supply noise spectral content to predict
the jitter generated by the supply noise. Jitter sensitivity is extracted by
sweeping the frequency of single tone disturbance added to the ideal supply.
Supply noise and jitter sensitivity are also measured by auto-correlation-based
on-chip noise monitor circuit. The predicted supply noise induced jitter is
shown to correlate well with the measurement data for a high speed I/O
interface operating at 6.4Gbps.
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