On-Chip Inductance Modeling and RLC Extraction of VLSI Interconnects for
Circuit Simulation
On-Chip inductance modeling of VLSI interconnects based on
Synopsys Arcadia database is
presented which captures 3-D geometry from layout designs
and technology information. Analytical formulae for self/mutual inductance
are derived for quick and accurate inductance estimation which can be used
in circuit simulations and whole chip extraction screening process.
Circuit simulations show critical global wire inductive effects as
well as power and ground inductive noise.
A paper was presented at
2000 IEEE Custom Integrated Circuits Conference
(CICC'00, May, 2000).