Leakage Current Optimization and Circuit Reliability Modeling



Sub-threshold leakage currents consume a significant fraction of total circuit power in 90 nm and 65 nm technologies. Generation of library cells for low leakage current is important for achieving low power ASIC designs. Since a typical ASIC library may contain thousands of cells, efficient techniques are required. In this project, a complete automated leakage optimization flow is presented. It includes an efficient circuit optimization engine to optimize device channel length and width while keeping cell delay increase and cell area change minimal. Optimization results show about 30% leakage current reduction with only several percent active area and dynamic power increase. The optimization flow starts with SPICE net-lists including parasitic RC extracted from the existing library. After leakage optimization, revised cell layouts are generated and characterized based on the optimized net-lists. In addition, investigations indicate that the optimization process has little impact on cell noise margins, and that new cell layout variations from placement, routing and compaction have little effect on the results. This efficient automated layout to layout cell leakage optimization flow is most suitable for leakage reduction and library migration for 90nm and 65 nm ASIC designs and beyond.

In deep sub-micron region, reliability issues that previously had little impact on circuits are becoming increasingly important. In this project, a simulation framework for reliability analysis of circuits in the SPICE environment has been proposed. The framework incorporates the degradation of physical parameters such as threshold voltage for PMOS transistors into circuit simulation and enables the design of highly reliable circuits.

Papers are to be published at the IEEE Circuits and Devices and ISQED'07.

  • "Efficient sub-threshold leakage current optimization and layout migration for 90nm and 65nm ASIC libraries," IEEE Circuits and Devices, Sep./Oct. 2006. Here is the paper.
  • "A new simulation method for NBTI analysis in SPICE environment," March, ISEQD'07.





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