Galerkin-Least-Squares finite-element methods have been used successfully for computational fluid dynamics. In this project a similar formulation for the hydrodynamic formulation of the semiconductor equations is being developed. We also intend to develop reliable and robust error estimators for the coupled system of elliptic Poisson and the hyperbolic advective-diffusive equations that constitute those required for device analysis. A quadtree/octree-based gridding scheme will be developed that supports the use of these error estimates.
The development of more flexible structure definition and gridding, based on the quadtree/octree methodology is being pursued as both an efficient data structure and one that can support parallelization. We derive the device geometry from a semiconductor wafer representation (SWR) and are developing robust gridding capabilities that support non-planar surfaces.
We are exploring the boundaries of both iterative and hybrid solution techniques in order to enhance the robustness of simulations over the complete range of biasing and device configurations. Specifically, parallel preconditioners and solvers for the iterative 3D methods are being developed for the case of general unstructured grid with generalized boundary conditions. In the case of 2D methods we are exploring robust direct methods in combination with iterative techniques that potentially extend the parallel scalability.
Based on a prototype of the 3D SWR (semiconductor wafer representation) combined with commercial layout, solid geometry modeling and visualization tools we have created 3D volumes and cross-sections that support TCAD device analysis of multi-transistor cells. Using newly developed 2D gridding capabilities and the HPC version of PISCES, multiple cross-sections of a cell have been analyzed. These same examples will be extended to the fully 3D grid and used to drive the 3D HPC device analysis capabilities.
Based on the very successful demonstrations of 3D bipolar simulations on the Delta Machine last year using interactive techniques and especially parallel ILU preconditioners, we are now developing a more complete library of those techniques for use with unstructured grid. The basic components are now being debugged and tested and the parallel domain and communication scheduling functions are being developed. In addition, the specification of arbitrary boundary conditions, including mixed circuit-device interactions, is being developed in support of both 2D and 3D device simulation.
Adaptive 1D gridding for the above GLS-FEM code has been initially demonstrated based on an error indicator using the Poisson equation.
Automated 2D gridding of arbitrary cross-sections derived from a fully 3D geometry model has been achieved using "wrappers" on commercial tools.
The PISCES-MP 2D code has been has been ported to a single node of the CM/5.
The prototype uses some of the most advanced numerical formulations as well as matrix techniques that are ideally suited for parallelization. The particular class of HD device equations is known to cause difficulties in achieving convergent solutions in the face of steep gradients (i.e. "shocks"). Using advances in GLS-FEM technology from the CFD domain, we have overcome these difficulties. Of equal and possibly greater potential is the fact that this prototype opens the way for other semiconductor modeling applications to further exploit GLS-FEM. One specific example to be considered in the SPRINT-CAD project is the simulation of thermal processing of semiconductors. This time-dependent problem involves especially difficult physics dictated by the coupling of stress with other kinetic effects such as impurity diffusion and oxide growth. Presently no robust formulation exists, even for the 2D case. The present results with the GLS-FEM method offer a very promising alternative to be investigated.
(Also, please see the SIGNIFICANT EVENTS section of the SPRINT-CAD Project Summary dealing with 3D GEOMETRY MODELING)