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Parastoo NikaeenPhD
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| Email: parastoo DOT nikaeen AT gmail DOT
com Tel: (650)804-5011 |
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Education Ph.D. Electrical Engineering, Stanford University, Stanford, CA (2004-2008) M.S. Electrical Engineering, Stanford University, Stanford, CA (2002-04) B.S. Electrical engineering, Sharif University of Technology, Tehran, Iran (1997-2001) Publications: P. Nikaeen , B. Murmann, “Digital Compensation of Dynamic Acquisition Errors at the Front-End of High-Performance A/D Converters”,IEEE J. Selected Topics in Signal Processing, vol. 3, no. 3, pp. 499-508, Jun. 2009
P. Nikaeen , B. Murmann, “Digital Correction of Dynamic Track-and-Hold Errors Providing SFDR > 83 dB up to fin = 470 MHz”,Proc. IEEE Custom Integrated Circuits Conference (CICC), pp. 161-164, Sept. 2008.
M. Jeeradit, J. Kim, B. Leibowitz, P. Nikaeen, V. Wang, B. Garlepp, C. Werner,“ Characterizing Sampling Aperture of Clocked Comparators”, VLSI Circuits Symposium, Digest of Technical Papers, pp. 68-69, June 2008.
P. Nikaeen , B. Murmann, R.W. Dutton, “Characterizing the Impact of Substrate Noise on High-Speed Flash ADCs”,Proc. International Symposium on Quality Electronic Design (ISQED), pp. 396-400, March 2008.
B. Murmann, P. Nikaeen, D.J. Connelly and R.W. Dutton, “Impact of Scaling on Analog performance and Associated Modeling Needs”, Electron Devices, IEEE Transaction on, Sept. 2006, pp 2160-2167.
H. Lan, T.W. Chen, C. Chui, P. Nikaeen, J.W. Kim and R.W. Dutton,” Synthesized compact model and experimental verifications for substrate noise coupling in mixed-signal ICs,” , IEEE Journal of Solid State Circuits, Aug. 2006, pp. 1817-1829
H. Lan, T.W. Chen, C. Chui, P. Nikaeen, J.W. Kim and R.W. Dutton,” Synthesized compact model and experimental results for substrate noise coupling in mixed-signal ICs,” Proc. IEEE Custom Integrated Circuits Conference (CICC), pp. 469-472, Sept. 2005.
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