Publications


Journal Papers

  1. Chuanzhao Yu, J. Zhang, J. S. Yuan, F. Duan, S. K. Jayanarananan, A. Marathe, S. Cooper, V. Pham, and J.-S. Goo, " Evaluation of RF Capacitance Extraction for Ultrathin Ultraleaky SOI MOS Devices," IEEE Electron Device Letters, Vol. 28, No. 1, pp. 45-47, Jan. 2007.
  2. Jung-Suk Goo, Tilo Mantei, Karsten Wieczorek, William G. En, and Ali B. Icel, " Extending Two-Element Capacitance Extraction Method Toward Ultraleaky Gate Oxides Using a Short-Channel Length," IEEE Electron Device Letters, Vol. 25, No. 12, pp. 819-821, Dec. 2004.
  3. C. Jungemann, N. Subba, J. -S. Goo, C. Riccobene, Q. Xiang, and B. Meinerzhagen, "Investigation of strained Si/SiGe devices by MC simulation," Solid-State Electronics, Vol. 48, No. 8, pp. 1417-1422, Aug. 2004.
  4. Jung-Suk Goo, Stephen Hale, Luis Zamudio, Mario M. Pelella, Richard Klein, Steven Butler, Judy Xilin An, Michael Lee, and Ali B. Icel, " Switching-Mode Dependence of Inductive Noise in VLSI Power Bus Lines," IEEE Electron Device Letters, Vol. 25, No. 5, pp. 302-304, May 2004.
  5. James Pan, Christy Woo, Minh-Van Ngo, James Xie, David Matsumoto, Dakshi Murthy, Jung-Suk Goo, Qi Xiang, and Ming-Ren Lin, " The Effect of Annealing Temperatures on Self-Aligned Replacement (Damascene) TaCN-TaN-Stacked Gate pMOSFETs," IEEE Transactions on Electron Devices, Vol. 51, No. 4, Apr. 2004, pp. 581-586.
  6. Jung-Suk Goo, Qi Xiang, Yayoi Takamura, Farzad Arasnia, Eric N. Paton, Paul Besser, James Pan, and Ming-Ren Lin, " Band Offset Induced Threshold Variation in Strained-Si nMOSFETs," IEEE Electron Device Letters, Vol. 24, No. 9, pp. 568-570, Sep 2003.
  7. Jung-Suk Goo, Qi Xiang, Yayoi Takamura, Haihong Wang, James Pan, Farzad Arasnia, Eric N. Paton, Paul Besser, Maxim V. Sidorov, Ercan Adem, Anthony Lochtefeld, Glyn Braithwaite, Matthew T. Currie, Richard Hammond, Mayank T. Bulsara, and Ming-Ren Lin, " Scalability of Strained-Si nMOSFETs Down to 25nm Gate Length," IEEE Electron Device Letters, Vol. 24, No. 5, pp. 351-353, May 2003.
  8. Jung-Suk Goo, Hee-Tae Ahn, Donald J. Ladwig, Zhiping Yu, Thomas H. Lee, and Robert W. Dutton, " A Noise Optimization Technique for Integrated Low-Noise Amplifiers," IEEE Journal of Soide State Circuits, Vol. 37, No. 8, pp. 994-1002, Aug. 2002.
  9. Jung-Suk Goo, Chang-Hoon Choi, Antonio Abramo, Jae-Gyung Ahn, Zhiping Yu, Thomas H. Lee, and Robert W. Dutton, " Physical Origin of the Excess Thermal Noise in Short Channel MOSFETs," IEEE Electron Device Letters, Vol. 22, No. 2, pp. 101-103, Feb. 2001.
  10. Jung-Suk Goo, Chang-Hoon Choi, Francois Danneville, Eiji Morifuji, Hisayo Sasaki Momose, Zhiping Yu, Hiroshi Iwai, Thomas H. Lee, and Robert W. Dutton, " An Accurate and Efficient High Frequency Noise Simulation Technique for Deep Submicron MOSFETs," IEEE Transactions on Electron Devices, Vol. 47, No. 12, pp. 2410-2419, Dec. 2000.
  11. Chang-Hoon Choi, Yider Wu, Jung-Suk Goo, Zhiping Yu, and Robert W. Dutton, " Capacitance Reconstruction from Measured C-V in High Leakage, Nitride/Oxide MOS," IEEE Transactions on Electron Devices , Vol. 47, No. 10, Oct. 2000, pp. 1843-1850.
  12. Chang-Hoon Choi, Jung-Suk Goo, Zhiping Yu, and Robert W. Dutton, " Shallow Source/Drain Extension Effects on External Resistance in Sub-0.1 um MOSFET's," IEEE Transactions on Electron Devices , Vol. 47, No. 3, Mar. 2000, pp. 655-658.
  13. Chang-Hoon Choi, Jung-Suk Goo, Tae-Young Oh, Zhiping Yu, Robert W. Dutton, Amr Bayoumi, Min Cao, Paul Vande Voorde, Dieter Vook, and Carlos H. Diaz, " MOS C-V Characterization of Ultra-Thin Gate Oxide Thickness (1.3-1.8nm)," IEEE Electron Device Letters, vol. 20, no. 6, pp. 292-294, June 1999.
  14. H. Hwang, J.-S. Goo, H. Kwon, and H. Shin, " Anomalous Hot Carrier Degradation of nMOSFET's at Elevated Temperatures," IEEE Electron Device Letters , Vol. 16, No. 4, Apr., 1995, pp. 148-150.
  15. J.-S. Goo, Y.-G. Kim, H. l'Yee, H.-Y. Kwon, and H. Shin, "An Analytical Model for Hot-Carrier-Induced Degradation of Deep-Submicon n-Channel LDD MOSFETs," Solid-State Electronics , Vol. 38, No. 6, Jun., 1995, pp. 1191-1196.
  16. J.S. Goo, H. Shin, H. Hwang, D.G. Kang, and D.H. Ju, "Physical Analysis for Saturation Behavior of Hot-Carrier Degradation in Lightly Doped Drain N-Channel Metal-Oxide-Semiconductor Field Effect Transistors," Japanese Journal of Applied Physics , Part 1, Vol. 33, No. 1B, Jan., 1994, pp. 606-611.
  17. M.W. Park, D.G. Khang, J.S. Goo, Y.J. Park, " Charge to Breakdown Mechanism of Thin ONO Films," IEEE Transactions on Electron Devices , Vol. 37, No. 11, Nov., 1990, pp. 2419-2422.

    Conference Papers

  1. Q. Chen, S. Balasubramanian, C. Thuruthiyil, M. Gupta, V. Wason, N. Subba, J.-S. Goo, P. Chiney, S. Krishnan, and A. B. Icel, "Critical Current (Icrit) Based SPICE Model Extraction for SRAM Cell," Proceedings of the 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), Beijing, China, pp. 301-304, Oct. 2008.
  2. [Invited] Q. Chen, Z.-Y. Wu, T. Ly, M. Gupta, V. Wason, J.-S. Goo, C. Thuruthiyil, M. Radwin, N. Subba, P. Chiney, S. Suryagandh, and A. B. Icel, " Extraction of Speculative SOI MOSFET Models Using Self-Heating Free Targets," Proceedings of the 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), Beijing, China, pp. 284-287, Oct. 2008.
  3. Q. Chen, J.-S. Goo, T. Ly, K. Chandrasekaran, Z.-Y. Wu, C. Thuruthiyil, and A. B. Icel, " Off-State Leakage Current Modeling in Low-Power/High-Performance Partially-Depleted (PD) Floating-Body (FB) SOI MOSFETs," Proceedings of the 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), Beijing, China, pp. 448-451, Oct. 2008.
  4. J.-S. Goo, Q. Chen, A. Pandey, Y. Apanovich, T. Ly, V. Wason, N. Subba, C. Thuruthiyil, and A. B. Icel, "SPICE Parameter Extraction and RO Validation of a 65nm SOI Technology," Proceeding of the IEEE International SOI Conference, New Paltz, New York, USA, pp. 153-154, October 2008.
  5. [Invited] J.-S. Goo, R. Q. Williams, G. O. Workman, Q. Chen, S. Lee, and E. J. Nowak, " Compact Modeling and Simulation of PD-SOI MOSFETs: Current Status and Challenges," Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, pp. 265-272, Sep. 2008. (Slide)
  6. X. Xi, F. Li, B. Tudor, W. Wang, W. Liu, F. Lee, P. Wang, N. Subba, and J.-S. Goo, " An Improved Impact Ionization Model for SOI Circuit Simulation," Proceedings of WCM (Workshop on Compact Modeling), NSTI (Nano Science and Technology Institute) Nanotech, Boston, MA, Vol, 3, pp. 841-844, May 2008.
  7. S. Suryagandh, M. Gupta, Z.-Y. Wu, S. Krishnan, M. Pelella, J.-S. Goo, C. Thuruthiyil, J. X. An, N. Subba, L. Zamudio, J. Yonemura, and A. B. Icel, " Impact of Stress on Various Circuit Characteristics in 65nm PDSOI Technology," Ext. Abstracts of the 37th European Solid State Device Research Conference (ESSDERC), Munich, Germany, pp. 119-122, Sep. 2007.
  8. Q. Chen, S. Suryagandh, J.-S. Goo, J. X. An, C. Thuruthiyil, and A. B. Icel, " Impact of Gate Induced Drain Leakage and Impact Ionization Currents on Hysteresis Modeling of PD SOI Circuits," Proceedings of WCM (Workshop on Compact Modeling), NSTI (Nano Science and Technology Institute) Nanotech, Santa Clara, CA, Vol, 3, pp. 570-573, May 2007.
  9. Q. Chen, Z.-Y. Wu, R. Y. K. Su, J.-S. Goo, C. Thuruthiyil, M. Radwin, N. Subba, S. Suryagandh, T. Ly, V. Wason, J. X. An, and A. B. Icel, " Extraction of Self-Heating Free I-V Curves Including the Substrate Current of PD SOI MOSFETs," Proceedings of ICMTS (International Conference on Microelectronic Test Structures), Tokyo, Japan, pp. 272-275, March 2007.
  10. [Invited] V. Wason, J. An, J.-S. Goo, Z.-Y. Wu, Q. Chen, C. Thuruthiyil, R. Topaloglu, P. Chiney, and A. Icel, "Statistical Compact Modeling and Si Verification Methodology," Proceedings of ICSICT (International Conference on Solid-State and Integrated-Circuit Technology)}, Shanghai, China, E1.3, October 2006.
  11. Q. Chen, Z.-Y. Wu, A. B. Icel, J.-S. Goo, S. Krishnan, C. Thuruthiyil, N. Subba, S. Suryagandh, J. X. An, T. Ly, M. Radwin, J. Yonemura, and F. Assad, "On Idlow with Emphasis on Speculative SPICE Modeling," Proceedings of WCM (Workshop on Compact Modeling), MSM (Modeling and Simulation of Microsystems), Boston, MA, Vol. 3, pp. 831-834, May 2006.
  12. [Invited] J.-S. Goo, "Challenges and Strategies for the SPICE Model Extraction and Simulation of the PD-SOI Technology," MOS-AK Workshop for Principles and Practice of the Compact Modeling and its Standardization, Grenoble, France, Sep 2005.
  13. Qiang Chen, Jung-Suk Goo, Niraj Subba, Xiaowen Cai, Judy X. An, Tran Ly, Zhi-Yuan Wu, Sushant Suryagandh, Ciby Thuruthiyil, Martin Radwin, Luis Zamudio, James Yonemura, Farzin Assad, Mario M. Pelella, and A. B. Icel, "An A Priori Hysteresis Modeling Methodology for Improved Efficiency and Model Accuracy in Advanced PD SOI Technologies," Proceedings of Nano Science and Technology Institute Nanotechnology Conference & Trade Shows, Anaheim, CA, pp. 159-162, May 2005.
  14. Ciby Thuruthiyil, Judy An, Jung-Suk Goo, Niraj Subba, Qiang Chen, Sushant Suryagandh, and Ali Icel, "SOI Compact Modeling Strategies and Challenges for High Performance Logic Applications," Proceedings of APMC (Asia Pacific Microwave Conference), New Delhi, India, Session A12-2, p. 657, December, 2004.
  15. Jung-Suk Goo, Judy Xilin An, Ciby Thuruthiyil, Tran Ly, Qiang Chen, Martin Radwin, Zhi-Yuan Wu, Michael S. L. Lee, Luis Zamudio, James Yonemura, Farzin Assad, Mario M. Pelella, and Ali B. Icel, "History-Effect-Conscious SPICE Model Extraction for PD-SOI Technology," Proceeding of the IEEE International SOI Conference, Charleston, South Carolina, USA, pp. 156-158, October 2004.
  16. Q. Xiang, J.-S. Goo, J. Pan, B. Yu, S. Ahmed, J. Zhang, and M.-R. Lin, " Strained Silicon NMOS with Nickel-Silicide Metal Gate," Proceedings of Symposium on VLSI Technology, Kyoto, Japan, pp. 101-102, June 2003.
  17. J. Pan, M.-V. Ngo, C. Woo, J.-S. Goo, P. Besser, B. Yu, Q. Xiang, and M.-R. Lin, " Metal Gate NMOSFETs with TaSiN/TaN Stacked Electrode Fabricated by a Replacement (Damascene) Technique," Proceedings of VLSI-TSA (International Symposium on VLSI Technology, Systems, and Applications), Hsinchu, Taiwan, ROC, T24, April, 2003.
  18. Q. Xiang, J.-S. Goo, H. Wang, Y. Takamura, B. Yu, J. Pan, A. Nayfeh, A. Holbrook, F. Arasnia, E. Paton, P. Besser, M. Sidorov, E. Adem, A. Lochtefeld, G. Braithwaite, M. Currie, R. Hammond, M. T. Bulsara, and M.-R. Lin, " 25nm Gate Length Strained Silicon CMOS," Abstracts of ISTDM (International SiGe Technology and Device Meeting), Nagoya, Japan, pp.13-14, January, 2003.
  19. W. P. Maszara, Z. Krivokapic, P. King, J.-S. Goo, and M.-R. Lin, " Transistors with Dual Work Function Metal Gates by Single Full Silicidation (FUSI) of Polysilicon Gates," Technical Digest of IEDM (International Electron Devices Meeting), San Francisco, CA, USA, pp. 367-370, December, 2002.
  20. J. Zhang, E. Zhao, Q. Xiang, J. Chan, J. Jeon, J.-S. Goo, A. Marathe, B. Ogle, M.-R. Lin, and K. Taylor, " Polarity Dependent Reliability of Advanced MOSFET Using MOCVD Nitrided Hf-Silicate High-k Gate Dielectric," IRW (International Integrated Reliability Workshop), S. Lake Tahoe, CA, USA, #HKD-1, October, 2002.
  21. Jung-Suk Goo, Hee-Tae Ahn, Donald J. Ladwig, Zhiping Yu, Thomas H. Lee, and Robert W. Dutton, " Design Methodology for Power-Constrained Low Noise RF Circuits," Proceedings of the Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), Nara, Japan, pp. 394-401, October 2001.
  22. Jung-Suk Goo, Simona Donati, Chang-Hoon Choi, Zhiping Yu, Thomas H. Lee, and Robert W. Dutton, " Impact of Substrate Resistance on Drain Current Noise in MOSFETs," Proceedings of International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Athens, Greece, pp. 182-185, September 2001.
  23. Jung-Suk Goo, William Liu, Chang-Hoon Choi, Keith R. Green, Zhiping Yu, Thomas H. Lee, and Robert W. Dutton, " Equivalence of van der Ziel and BSIM4 Models in Modeling the Induced Gate Noise of MOSFETs," Technical Digest of IEDM (International Electron Devices Meeting), San Francisco, pp. 811-814, December 2000.
  24. Jung-Suk Goo, Kwang-Hoon Oh, Chang-Hoon Choi, Zhiping Yu, Thomas H. Lee, and Robert W. Dutton, " Guidelines for the Power Constrained Design of a CMOS Tuned LNA," Proceedings of International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Seattle, WA, USA, pp. 269-272, September 2000.
  25. Chang-Hoon Choi, Kwang-Hoon Oh, Jung-Suk Goo, Zhiping Yu, and Robert W. Dutton, " Direct Tunneling Current Model for Circuit Simulation," Technical Digest of IEDM (International Electron Devices Meeting), Washington DC, pp. 735-738, December 1999.
  26. Jung-Suk Goo, Chang-Hoon Choi, Francois Danneville, Zhiping Yu, Thomas H. Lee, and Robert W. Dutton, " Issues in High Frequency Noise Simulation for Deep Submicron MOSFETs," Proceedings of the International Conference on Unsolved Problems of Noise and Fluctuations (UPoN), American Institute of Physics, Adelaide, Australia, pp. 401-406, July 1999.
  27. Jung-Suk Goo, Chang-Hoon Choi, Eiji Morifuji, Hisayo Sasaki Momose, Zhiping Yu, Hiroshi Iwai, Thomas H. Lee, and Robert W. Dutton, " RF Noise Simulation for Submicron MOSFET's Based on Hydrodynamic Model," Proceedings of Symposium on VLSI Technology, Kyoto, Japan, pp. 153-154, June 1999.
  28. Chang-Hoon Choi, Jung-Suk Goo, Tae-Young Oh, Zhiping Yu, Robert W. Dutton, Amr Bayoumi, Min Cao, Paul Vande Voorde, Dieter Vook, and Carlos H. Diaz, " C-V and Gate Tunneling Current Characterization of Ultra-Thin Gate Oxide MOSFET (tox=1.3-1.8 nm)," Proceedings of Symposium on VLSI Technology, Kyoto, Japan, pp. 63-64, June 1999.
  29. H. Lee, Y. Huh, J.-S. Goo, S.-D. Lee, D. Yang, and W. Kim, " A New Leakage Component Caused by the Interaction of Residual Stress and the Relative Position of Poly-Si Gate at Isolation Edge," IEEE International Electron Devices Meeting (IEDM), Washington D.C., USA, Dec., 1995, pp. 683-686
  30. H. Hwang, J.-S. Goo, H. Kwon, and H. Shin, " Impact of Velocity Saturation Region on nMOSFET's Hot-Carrier Reliability at Elevated Temperatures," IEEE International Reliability Physics Symposium (IRPS), Las Vegas, Nevada, USA, Apr. 3-6, 1995, pp. 48-50.
  31. H. Hwang, J.-S. Goo, H. Kwon, and H. Shin, " Enhanced Degradation of nMOSFET's under Hot Carrier Stress at Elevated Temperatures Due to The Length of Velocity Saturation Region," IEEE International Integrated Reliability Workshop (Former the Wafer Level Reliability Workshop), Final Report, Lake Tahoe, California, USA, Oct. 16-19, 1994, pp. 69-72.
  32. H. Hwang, J.-S. Goo, H. Kwon, and H. Shin, "Anomalous Temperature Dependence of nMOSFET Lifetime under Hot Electron Stress," Ext. Abstracts of the 24th European Solid State Device Research Conference (ESSDERC), Edinburgh, United Kingdom, Sept. 11-15, 1994, pp. 381-384.
  33. J.-S. Goo, Y.-G. Kim, H. l'Yee, H.-Y. Kwon, and H. Shin, "An Analytical Hot-Carrier Degradation Model for LDD NMOSFETs," Ext. Abstracts of the 24th European Solid State Device Research Conference (ESSDERC), Edinburgh, United Kingdom, Sept. 11-15, 1994, pp. 425-428.
  34. H. Hwang, J.-S. Goo, H. Kwon, and H. Shin, "Impact of Oxide Electric Field on Hot-carrier Reliability Characteristics," 184th Meeting of the Electrochemical Society, New Orleans, Louisiana, USA, Oct. 10-15, 1993, Late News.
  35. J.S. Goo, H. Shin, H. Hwang, D.G. Kang, and D.H. Ju, "Universal Behavior of Hot-Carrier Degradation in LDD NMOSFET's," Ext. Abstracts of the 1993 Conference on Solid State Devices and Materials (SSDM), Chiba, Japan, Aug. 29-Sept. 1, 1993, pp. 35-37.
  36. Y.G. Kim, J.S. Goo, H. l'Yee, H. Hwang, and H. Shin, "Charge-up Induced Gate Oxide Breakdown," Proceedings of International Workshop on Process and Devices of Scaled LSI's, Seoul, Korea, June 24-25, 1993, pp. 64-68.


Patents


  1. Q. Xiang, H. Zhong, J.-S. Goo, A. K. Holbrook, J. S. Jeon, and G. J. Kluth, "CMOS gates formed by integrating metals having different work functions and having a high-k gate dielectric," US Patent No. 7,176,531, February 13, 2007.
  2. Q. Xiang, J.-S. Goo, and H. Wang, "Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and method for its fabrication," US Patent No. 7,170,084, January 30, 2007.
  3. Q. Xiang, J. N. Pan, , and J.-S. Goo, "Method of fabricating an integrated circuit channel region," US Patent No. 7,138,302, November 21, 2006.
  4. W. P. Maszara, J.-S. Goo, J. N. Pan, and Q. Xiang, "Formation of finFET using a sidewall epitaxial layer," US Patent No. 7,078,299, July 18, 2006.
  5. Q. Xiang, J.-S. Goo, and J. N. Pan, "Strained silicon semiconductor on insulator MOSFET," US Patent No. 7,033,869, April 25, 2006.
  6. Q. Xiang, J.-S. Goo, and J. Pan, "Silicon on insulator substrate having improved thermal conductivity and method of its formation," US Patent No. 7,015,078, March 21, 2006.
  7. J.-S. Goo, Q. Xiang, and J. Pan, "Strained silicon MOSFET having improved thermal conductivity and method for its fabrication," US Patent No. 7,012,007, March 14, 2006.
  8. M.-V. Ngo, M.-R. Lin, E. N. Paton, H. Wang, Q. Xiang, and J.-S. Goo, "Shallow trench isolation process using oxide deposition and anneal," US Patent No. 6,962,857, November 8, 2005.
  9. I. J. Djomehri, J.-S. Goo, S. Krishnan, W. P. Maszara, J. N. Pan, and Q. Xiang, "Method of growing as a channel region to reduce source/drain junction capacitance," US Patent No. 6,955,969, October 18, 2005.
  10. Q. Xiang, J.-S. Goo, J. N. Pan, and M.-R. Lin, "Semiconductor on insulator MOSFET having strained silicon channel," US Patent No. 6,943,087, September 13, 2005.
  11. J.-S. Goo, Q. Xiang, and J. N. Pan, "Replacement gate strained silicon finFET process," US Patent No. 6,936,516, August 30, 2005.
  12. I. J. Djomehri, Q. Xiang, J.-S. Goo, and J. N. Pan, "Strained silicon MOSFETs having NMOS gates with work functions for compensating NMOS threshold voltage shift," US Patent No. 6,929,992, August 16, 2005.
  13. Q. Xiang, J.-S. Goo, and H. Wang, "Semiconductor device having a thick strained silicon layer and method of its formation," US Patent No. 6,902,991, June 7, 2005.
  14. J. N. Pan, J.-S. Goo, and Q. Xiang, "Strained silicon MOSFETs having improved thermal dissipation," US Patent No. 6,900,143, May 31, 2005.
  15. Q. Xiang, H. Zhong, J.-S. Goo, A. K. Holbrook, J. S. Jeon, and G. J. Kluth, "Method for integrating metals having different work functions to form CMOS gates having a high-k gate dielectric and related structure," US Patent No. 6,872,613, March 29, 2005.
  16. M. V. Ngo, M.-R. Lin, P. R. Besser, Q. Xiang, E. N. Paton, and J.-S. Goo, "Depletion to avoid cross contamination," US Patent No. 6,858,503, February 22, 2005.
  17. M.-R. Lin, J.-S. Goo, H. Wang, and Q. Xiang, "FinFET device incorporating strained silicon in the channel region," US Patent No. 6,800,910, October 5, 2004.
  18. Q. Xiang, J.-S. Goo, and H. Wang, "Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and method for its fabrication," US Patent No. 6,756,276, June 29, 2004.
  19. H. Wang, P. R. Besser, J.-S. Goo, M. V. Ngo, E. N. Paton, and Q. Xiang, "Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer." US Patent No. 6,730,576, May 4, 2004.
  20. Jung-Suk Goo, "Method for isolating elements in a semiconductor device," US Patent No. 5,821,145 , Oct. 13, 1998.
  21. Jung Suk Goo, "Method of fabricating a nonvolatile semiconductor memory device," US Patent No. 5,677,215 , Oct. 14, 1997.
  22. Jung S. Goo, "Nonvolatile semiconductor memory device," US Patent No. 5,477,072 , Dec. 19, 1995.
  23. Goo Jung-Suk, "Process for formation of LDD transistor, and structure thereof," US Patent No. 5,389,557 , Feb. 14, 1995.
  24. Jung S. Goo, "Method of Making Metal Oxide Semiconductor Field Oxide Transistor," US Patent No. 5,328,862 , Jul. 12, 1994.
  25. Goo Jung-Suk, "Process for Formation of LDD Transistor, and Structure thereof," US Patent No. 5,262,664 , Nov. 16, 1993.

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