Educations

• Stanford University, California, USA (PhD) 1997-2001
  
  
• Stanford University, California, USA (MS) 1995-1997
  
  
• Yonsei University, Seoul, Korea (BSEE) 1984-1987
  
  

Professional Careers

• GLOBALFOUNDRIES, Sunnyvale, CA 2009-
  - Advanced modeling & characterization issues
  - Passive modeling
  
  
• AMD, Sunnyvale, CA 2002-2009
  - Advanced modeling characterization issues
  - High-k Dielectric Process Integration
  - Biaxial strained-Si Process Integration
  
  
• Atheros Communications, Sunnyvale, CA 2001
  - BSIM4 Model Evaluation
  - IEEE 802.11a Radio Chip Development
  
  
• AMD, Sunnyvale, CA 2001
  - Gate Capacitance Restoration Modeling for Ultra-thin Dielectrics
  - 35nm CMOS Process Development
  
  
• LG Semicon Co., ChungJu, Korea 1995
  - 0.3um CMOS Process for 256M DRAM
  - 0.25um Isolation Process for 256M DRAM
  
  
• GoldStar Electron Co., Seoul, Korea 1990-1994
  - 0.5um CMOS Process for 64M DRAM
  - 1.2um CMOS Process for 1M Flash Memory
  
  
• GoldStar Semiconductor Co., Anyang, Korea 1988-1989
  - 2.0um CMOS Process for 64K High Speed EPROM
  - 1.0um CMOS Process for 4M DRAM
  
  

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Home Page of Jung-Suk Goo