Guidelines for the Power Constrained Design of a CMOS Tuned LNA
Published in the Proceedings of International Conference on Simulation of
Semiconductor Processes and Devices (SISPAD), Seattle, WA, USA, pp. 269-272,
Sep. 2000.
Based on extensive high-frequency noise simulations for a
0.25um nMOSFET for the entire operating range,
this paper presents explicit design guidelines for
a CMOS tuned LNA, given a power constraint.
The noise behavior of the LNA cannot simply be described based on the
conventional Fmin-Rn-Yopt representation.
The best noise figure is achieved by optimizing the source inductance
and its value is much lower than NFmin, regardless of the current
specification. When the choice of the source inductance is
restricted, the simultaneous choice of gate bias and device width
is very critical. Nonetheless noise figure lower than NFmin can still
be achieved. Usually, for 50Ohm input match, the best
noise figure is realized in a bias range of 0.1~0.3V above
the threshold voltage, depending on the power specification.
The noise contribution of a cascoding device is usually not significant and
its optimal width is about equal to that of the input device.
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