Design Methodology for Power-Constrained Low Noise RF Circuits
Published in the Proceedings of the Workshop on Synthesis and System
Integration of Mixed Technologies (SASIMI), Nara, Japan, pp. 394-401,
Oct. 2001.
Based on measured four-noise parameters and two-port noise theory, guidelines
for integrated LNA (low noise amplifier) design are presented.
If arbitrary values of source impedance are allowed, an optimal LNA
design is obtained by adjusting the source degeneration inductance.
Even for a fixed source impedance, the integrated LNA can
achieve near NFmin by choosing an appropriate device geometry
along with an optimal bias condition.
An 800MHz LNA has been implemented in a standard 0.24um CMOS technology.
The amplifier possesses a 0.9dB noise figure while drawing 7.5mW
from a 2.0V power supply, demonstrating that the proposed methodology
can accurately predict noise performance of integrated LNA designs.
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