A Noise Optimization Technique for Integrated Low Noise Amplifiers
IEEE Journal of Solid State Circuits, Vol. 37, No. 8,
pp. 994-1002, Aug. 2002.
Based on the measured noise parameters of the 0.24um MOSFET,
and on the results derived from noisy two-port theory, explicit guidelines
for a fully integrated LNA design are presented. The measured noise
parameters can be scaled directly with the device width; device sizing can
be utilized for power-constrained design.
The noise performance of the tuned LNA is primarily controlled by
the source degeneration inductance, which determines both the power matching
and the noise matching conditions. Therefore, if arbitrary values
of source impedance are allowed, the optimal LNA design can be obtained by
adjusting the source inductance.
Even if the source impedance is fixed, the fully integrated LNA can
achieve noise performance near NFmin by choosing an appropriate
device geometry and optimizing the bias conditions. The cascode
stage usually introduces at least 40% extra noise power to the input stage;
thus its width needs to be optimized.
Although the demonstrated LNA uses a single-ended architecture, future
LNA designs will require differential operation since further scaling
of the device sizes requires smaller values of source inductance.
Fully integrated inductors with large values and high Q-factors, required
for Lg, are an ongoing challenge.
The results demonstrate that CMOS can be a good candidate for high
performance LNA designs, competitive with GaAs and bipolar LNAs.
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