Model Abstraction for Circuit Simulation

Compact device models used in circuit simulation remain as the base of the electronic CAD design system, since it is the first abstraction level above the spatial coordinates. Yet compact models were less useful in consideration of predictive designs during technology evolution owing to many nonphysical fittings for the purpose of accuracy. In recent years as the computational resources become more powerful and accessible, technology CAD tools and environment have grown mature on their usage and calibration in the device level. However, on a circuit-module level (typically 500 to 10,000 circuit elements), TCAD tools, even though they can be presumed as very accurate and predictive, are still much too expensive. The abstraction step toward compact models must be applied. Traditionally, parameter extraction for compact models is based on optimal fit of IV or CV data obtained from lab measurements or simulated TCAD terminal characteristics. The number of circuit elements inside the compact model is usually fixed and the linkage hardwired. This procedure will lose most of the insight and sensitivity of the detailed profile information provided by the TCAD simulations.

An alternative method for model extraction is proposed. We propose an alternative method for parameter extraction. Given the solution profiles from device simulators, a more flexible and physically transparent compact model can be constructed accordingly. The values of these circuit elements are bias (or state) dependent (nonlinear resistors and capacitors), but advanced circuit simulators which provide two-terminal table-lookup and/or nonlinear parameter calculations can take these inputs with little extra efforts. This approach has the following advantages over the conventional method of optimal fitting:

  1. the linkage and the number of circuit elements is not hardwired.
  2. the error in device simulation parameters (such as mobility) can be directly reflected on the circuit element parameters (such as resistance).
  3. the circuit elements are physically transparent. The improvement of compact models can be done in an automatic, evolutionary way, based on the the progress of the device simulation.
Edwin Kan (kan@gloworm.Stanford.EDU)
AEL 201
Integrated Circuits Laboratory
Stanford University
Stanford, CA 94305-4055