Ph.D. Theses
- ESD Design Challenges and Strategies in Deeply-Scaled Integrated Circuits
-Shuqing Cao
- A Physics-Based Design Methodology for Digital Systems Robust to ESD-CDM Events
-Tze Wee Chen
- Digital Compensation of Dynamic Acquisition Errors at the Front-End of ADCs
-Parastoo Nikaeen
- Measurement, Suppression, and Prediction of Digital Switching Noise Coupling in Mixed-Signal System-on-Chip Applications
-Cosmin Iorga
- ESD Protection Circuits for Advanced CMOS Technologies
-Jung-Hoon Chun
- Amplitude and Phase Noise in Modern CMOS Circuits
-Reza Navid
- Synthesized Compact Models for Substrate Noise Coupling in Mixed-Signal ICs
-Hai Lan
- Geometric Algorithms and Software Architecture for Computational Prototyping: Applications in Vascular Surgery and MEMS
-Nathan Marshall Wilson
- Virtual-Ground Sensing Techniques for Fast, Low-Power, 1.8V Two-bit-per-cell Flash Memories
-Binh Quang Le
- Digital Noise Emulator for Characterization of Phase-Locked-Loop Systems Exposed to Substrate Noise
-Yi-Chang Lu
- Small-Signal Modeling of RF CMOS
-Jaejune Jang
- AC and Noise Analysis of Deep-submicron MOSFETs
-Tae-Young Oh
- Analysis, Design, and Optimization of Integrated High-Current Devices in High-Speed and Radio-Frequency Semiconductor Systems
-Choshu Ito
- Impact of Extension Lateral Doping Abruptness on Deep Submicron Device Performance
-Michael Y. Kwong
- Investigation of ESD Performance in Advanced CMOS Technology
-Kwang-Hoon Oh
- Modeling and Characterezation of Substrate Resistance for Deep Submicron ESD Protection Devices
-Xin Yi Zhang
- Modeling of Nanoscale MOSFETs
-Changhoon Choi
- Level Set Methods for Computational Prototyping with Application to Hemodynamic Modeling
-Kenneth Chung-Yi Wang
- Atomic Scale Modeling of Silicate Interface Properties for High-K Gate Dielectric Applications
-Atsushi Kawamoto
- High Frequency Characterization and Modeling of On-Chip Interconnects and RF IC Wire Bonds
-Xiaoning Qi
- High Frequency Noise in CMOS Low Noise Amplifiers
-Jung-Suk Goo
- Coupled Electromagnetic and Device Level Investigations of Metal-Insulator-Semiconductor Interconnects
-Gaofeng Wang
- Characterization and Modeling of Electrostatically Actuated Polysilicon Micromechanical Devices
-Edward Keat Leem Chan
- A Dial-An-Operator Approach to Simulation of Impurity Diffusion in Semiconductors
-Daniel W. Yergeau
- Characterization, Modeling and Design of ESD Protection Circuits
-Stephen Beebe
- Boundary Movement in Semiconductor Etching and Deposition Simulation
-Ze-Kai Hsiau
- Frequency Domain Algorithms for Simulating Large Signal Distortion in Semiconductor Devices
-Boris Troyanovsky
- A Methodology for the Parallelization of PDE Solvers: Application to Semiconductor Device Physics (tar and compressed file)
- Bruce P. Herndon
- Advanced Mobility Model for Design and Simulation of Deep Submicrometer MOSFETs
- Aon Mujtaba
- Experimental Investigation and Modeling of the Effects of High Dose Ion Implantation Damage on Boron Diffusion Silicon (Electronic copy not available)
- Robert Huang
- On Numerical Modeling of Thermal Oxidation in Silicon
- Vinay Rao
- Mesh Generation and Information Model for Device Simulation
- Dan Yang
- Grid and Geometry Servers for Semiconductor Process Simulation (compressed file)
-Zak Sahul
- Experiments and Simulations of Gallium Arsenide MESFET Sidegating Effects
-Yi Liu
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