This project addresses modeling and simulation of noise in advanced silicon-based devices, with special emphasis on hetero-junction transistors. The increased frequency performance of both HFET and HBT transistors fabricated in silicon hold great promise for high-frequency RF applications. However, the noise properties and how they scale with device dimensions are of paramount importance. This project, jointly with collaborators in Germany (Profs. Meinerzagen and Jungemann) exploits both Monte Carlo (MC) and Hydro-Dynamic (HD) device simulators to characterize noise properties in advanced Silicon-Germanium hetero-junction transistors as well as in conventional CMOS. Several CIS Partner companies are supporting and collaborating in this project-currently Philips, Matsushita and Infineon.
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Last updated August 5, 2004.
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