Electrostatic discharge (ESD) is one of the most important reliability problems in the IC industry today. It is responsible for about one-third of the field failures. Building test structures on silicon is the current design methodology of ESD protection circuits. For the same structure, the performance of the protection circuit is layout dependent. To improve the design methodology, new simulation models are being developed to analyze the layout of the protection structures.

Progress:

Measurements were taken on AMD's five 0.35um test devices. The five devices have two geometrical variations: Gate length variation and source/drain length variation. The trends in the experimental data for each variation were observed, and can be explained qualitatively due to the difference in avalanche multiplicative factor, Beta of BJT, and substrate resistance, which vary depending on the geometry features of the test devices. Next, the compact model coefficients are extracted using the calibration method according to Shiang's '97 SISPAD paper.

Publications & Presentations this Quarter:

Shiang L. Lim, Xin Y. Zhang, Zhiping Yu, Stephen Beebe, and Robert W. Dutton, "A Robust Quasi-Empirical Compact Model for the simulation of MOS Breakdown in ESD-Protection Circuit Design", Int'l Conf. on Simulation of Semiconductor Processes and Devices (SISPAD '97), Sept. 1997.

Trips:

Xin Yi attended the 1997 ESD Symposium in Santa Clara from Sept. 21-5. She also attended the 1997 GFP Annual Conference in Santa Clara from Sept. 28-30.