Xiaoning's research focus is to model the backend electrical behaviors for digital and analog ICs through a unified geometry representation extracted from layout and technology recipes. Recently, he is looking into the RF circuit's package parasitics modeling.

Progress:

Improvement has been made to ERSURF which is a bonding wires' indutance analysis tool for RF device's package. ERSURF now can generate capacitance analysis input file for Fastcap as well. At the same time, modeling package parasitics and local interconnects using more realistic, complex shapes is under investigation. It is expected in the next quarter that we can successfully analyse the capacitance of a very realistic and complex shape cells' local interconnects and package parasitics.

Publications & Presentations this Quarter:

Trips: None