Explore an efficient parametric representation to describe geometry extracted from the layout and the technology recipes. The idea is to provide an efficient way to transfer/store geometric information without scarifying too much in accuracy.

Progress:

Simple single wire interconnect model has been built using bspline function in ACIS. A more complete model is going to be built and further performance comparision will be made using fastcap.

Publications & Presentations this Quarter: None

Trips: None