1) Complete the development of an unified information model that provides framework-based interfacing of layout and solid geometry with process flow information and ultimately the Semiconductor Process Representation (SPR) when it is fully developed.
The primary focus of the information model development efforts has been to extend the SWR specification to support fully 3D information and to use commercially available tools to test several aspects of these information models. Namely, the Cadence tool has been used to derive mask layout information. Based on extensions of the interim Version 1.5 of the SWR (developed and documented by Dawn Technology as part of an SBIR) we have created 3D extensions. The ACIS tool from Spatial Technology has been used as a geometry modeling engine, based on creation of a husk to interface with the SWR information model. This geometry representation of the data can then be: visualized (using AVS), cross-sectioned for subsequent 2D gridding or selective material layers choosen for surface meshing as required by the parasitic capacitance extractor FASTCAP (developed at MIT by Professor White and his students). The result of this effort is the ability to go from mask information to several derivative models for the devices, circuits or interconnects represented by the layout. In the third item of this section we consider more specifically the applications of these models. From an information model point of view, this phase of the work has clarified the information modeling issues of creating a 3D SWR and as a by-product we have created specific applications that are useful for device and circuit modeling.
2) Complete the development of an automated gridding strategy that provides support for both 2D tools such as SUPREM and PISCES as well as new capabilities to support emerging 3D device analysis tools.
As presented in the previous sub-task, using the 3D information model created using the extended SWR and ACIS arbitrary 2D cross-sections can be selected. Two sets of 2D gridding tools, both based on quad-tree algorithms, have been developed. In the context of the PISCES tool for 2D device analysis, we have extended the MESHBUILD tool (developed at ETH, Zurich by Professor Fichtner and his students) so that non-planar surfaces can be considered [Yang, VPAD]. In addition, we have created a level-control function to minimize the problems of excessive grid refinement based on small feature sizes [Yang, NUPAD 92]. In the context of the present work, we have tested this gridding tool extensively using both the SRAM example discussed below as well as for other examples developed in association with use of SEWB. In the area of 3D gridding we have extended the techniques mentioned above based on the octree formulation and a tool is being developed in support of our HPC efforts in adaptive FEM solvers.
The other quad-tree gridding program, called "Forest", was developed in support of both SUPREM and PISCES and is specifically targeted at complex 2D structures. Multi-layer devices with intricate features and layer structures have been gridded using Forest and documentation of the heuristics have been presented at SISDEP '93 [Sahul, SISDEP] and at TECHCON '93 [Sahul,TECHCON]. In addition, the Forest code is being tested as both an internal data structure for SUPREM as well as a stand-alone geometry-server for codes such as SPEEDIE (see other task). Both Forest and the enhanced MESHBUILD tools have been shown to provide robust 2D grids in a highly automated way. In both cases, the derived 2D cross-sections of regions and their associated material properties is all that is required in order to create high quality grid for direct use by PISCES. In the case of Forest the tool is used both as a grid- and geometry-server for 2D process simulation.
3) Applications have been created using the above capabilities that demonstrate tool utility for several classes of circuit, device and process problems. In addition, the simulation environment now supports distributed execution of SUPREM and PISCES for both statistical analysis and "auto calibration" purposes.
The primary set of applications pursued during this year have focused on demonstrating the ability to go all the way from mask layout to behavior level models. The most advanced demonstration of these capabilities is for a six transistor static RAM cell (6T SRAM) with associated perepheral circuitry. Based on the Cadence layout information of the cell, the full 3D model is created using the prototype SWR and ACIS tools (see Figure 1). From this 3D geometry model we have derived and gridded two representations used for behavioral analysis. The cross-sections in 2D for the resulting 6T cell core devices were gridded and analyzed using a mixed-mode PISCES/SPICE simulation to extract read/write behavior of the cell at the device level--the perepheral circuity was modeled at the SPICE level. The other representation was the full 3D model of the interconnect layers that was extracted and surface-gridded for analysis using FASTCAP. Based on these results the 3D parasitic capacitances of the cell could be extracted for use in the mixed-mode simulations. Taken as a whole this demonstration shows not only the power of the 3D information modeling approach but also the utility of the supporting tools to provide behavioral models that go beyond the commercial TCAD and ECAD state-of-the-art.
We have also continued to pursue the issues of calibration of TCAD tools in an effort to achieve "auto calibration" of simulators. This has involved two supporting efforts: distributed (ie parallel) execution of simulations and better means of tool control and data fitting. The efforts in supporting distributed execution of tools has been supported through the MMST program where Stanford was a sub-contractor to TI. We have developed task controllers that run in both a workstation environment as well as on dedicated parallel processors such as the Intel iPSC/860. Based on these capabilities we have demonstrated the ability to rapidly calibrate new physical models in SUPREM using heterogenous data sets (ie both our own data and other information from the literature) [Huang, ECS '93] [Dutton, SISDEP]. In the case of device analysis there have been major advances in the utilities to control PISCES and the methodology for calibration of the mobility models. Specifically, the algorithms for "curve tracing" have now been tested on a number of devices that exhibit severe nonlinearities (ie negative differential resistance) and documented in a publication [Beebe, IEEE]. In the case of mobility model calibration, we have worked collaboratively with Intel and further developed the BSIMJr tool as a means to accurately extract coefficients from both experimental data as well as from PISCES simulations [Dutton, SISDEP].
[2] D. Yang, K. Law, and R. W. Dutton, ``Optimal Moving Meshes for Process and Device Simulation,''NUPAD IV (Numerical Process and Device Modeling Workshop) Digest, pp. 181-186. Seattle, May 31--June 1, 1992.
[3] Z. Sahul, R. W. Dutton, M. Noell, ``Grid and Geometry Techniques for Multi-Layer Process Simulation,'' SISDEP Proceedings, Vienna, Austria, September 7-9, 1993.
[4] D. Yang, R. W. Dutton, K. H. Law, ``Delta-Zone Triangulation: A Boundary Refinement Scheme for Quadtree Based Mesh, 1993 International Workshop on VLSI Process and Device Modeling (1993 VPAD) Digest, pp. 120-121, Nara Japan, May 14-15, 1993.
[5] Z. Sahul, E. McKenna, R.W. Dutton, ``Grid Techniques for Multi-Layer Device and Process Simulation,'' TECHCON '93, Sept. 28-30, 1993, Atlanta, GA.
[6] R. Y. S. Huang, and R. W. Dutton, ``The Effect of Amorphizing Implants on Boron Diffusion,'' Presented 1993 Elecrochemical Society Meeting, Honolulu, Hawaii, May 1993.
[7] R.J.G. Goossens, S. Beebe, Z. Yu, and R.W. Dutton, "An Automatic Biasing Scheme for Tracing Arbitrarily Shaped I-V Curves," @i(IEEE Trans. on Computer-Aided Design), to be published.