In this context the University of Illinois and Stanford University have been co-directors of NCCE between 1992-1999 and jointly have shared the responsibilities to meet the above objectives. Over this period there have been a range of projects, meetings and technical contributions on both sides.
Under NCCE Sponsorship the Stanford team has contributed in a number of areas, specifically targeted to support device scaling, the inter-related problems of process simulation and collaborative efforts with industry and the computational electronics community more broadly.
In the sub-quarter micron MOS regime, the gate oxide thickness is scaled aggressively and the channel doping has to be kept high to reduce the leakage (or stand-by) drain current. These two factors mandate consideration of the QM effect as one of the major effects in determining the critical device characteristics such as the threshold voltage and gate capacitance. In collaborating with HP Labs and with input from UT Austin's enhancement to PISCES, we have improved analytical models, first proposed by Philips Lab in the Netherlands (i.e the so-called van Dort model) as well as the Hansch model (developed at TUV), to account for the QM effects in both surface inversion and accumulation layers. The model has been implemented in Stanford's PISCES 2H version and the initial comparison between simulation and measurement for MOS capacitors with 30A oxide thickness shows excellent agreement in both threshold voltage and capacitance. Results of this work were presented at IEDM '96 by Dr. Zhiping Yu and co-workers from HP. Ongoing work in simulator developments in this area are covered under the ParaSCOPE Project funded by DARPA and using the PROPHET simulation tool. The scaling and atomic scale process modeling issues are covered under the NSF-sponsored DesCArtES project.
To improve the QM modeling capabilities and to broaden applications
from device simulation to compact modeling as well, we have investigated
several different approaches and the tunneling aspect in the thin gate oxide.
One approach, which has been implemented in our 1D device simulator (SEDAN),
is to combine the solutions of Poisson and Schroedinger equations. This
approach allows the detailed analysis of carrier distribution on different
quantized energy levels. The problems are the slow numerical
convergence and inability in conducting AC analysis. We are continuing to
investigate algorithms to evaluate Jacobian matrix (i.e. derivatives) foreign
value solvers, which will eventually lead to a Newton-Raphson solver thus
possessing complete capabilities of both DC and AC analyses. More recently,
the NEMO simulator (developed at TI under a DARPA contract) has been
used to extract tunneling current information that is hierarchically embedded
in a lumped equivalent circuit model. This work was reported
at the 1999 VLSI Technology Symposium, IEEE EDL (Vol. 20, #6, p. 292, June
1999) and ongoing efforts in this area, sponsored under the DesCArtES
project, can be found in related work of Changhoon Choi towards his PhD
thesis.
Because it is anticipated that the tunneling will become significant for
gate oxide thickness below 30 to 40 A, we are continuing to investigate
the impact of the tunneling current through gate oxides, as well as
alternative gate-stack materials, on the MOS operation. This work involves
both the DesCArtES project activities in atomic-scale physical modeling
as well as links with the Nanomaterials (AT) activities
within NCSA--both ongoing NSF-sponsored projects.
Conventional scaling theories typically overlook the impact of parasitics such as the contact resistance in the source/drain contacts. As the dimension of MOS devices shrinks drastically, the delay of the intrinsic device becomes comparable with the delay caused by the parasitic RC elements. From the processing point of view, the contact resistance can only be reduced using novel technology but not completely eliminated. For the LDD structure, the resistance in the tip region (i.e. the lightly doped source/drain extensions) is also significant compared to the channel resistance. All these parasitical effects have to be carefully examined to accurately assess the performance improvement of MOS devices when the dimensions are scaled down.
A local, physics-based mobility model has been developed to account for the mobility degradation due to the gate bias in both inversion (i.e. channel) and accumulation (i.e. tip) regions. The model has been implemented in Stanford's PISCES 2H code and the simulation results are favorable in comparison with the experiment data from 0.25 mu (AT&T) and 0.35 mu (Cypress Semiconductor) CMOS technologies. For further details, see the 1995 VLSI Symposium paper as well as PhD thesis of Aon Mujtaba. More recent and ongoing contributions of Changhoon Choi continue to address ssues of coordinated scaling of both gate dielectric and source/drain regions in MOS devices.
For the impact of contact resistance on the MOS scaling, the 3D device simulator from IBM (Fielday) has been used to look at the effect of different layout designs. The 3D nature of this problem helps our research focus shift to more advanced simulation tools and to resolve the urgent concerns raised by industry. More recently, under SRC sponsorship, Ms. Xin Yi Zhang is considering 3D resistance effects on ESD protection circuits.
Progress has been made in developing macroscopic device models with the help of microscopic simulation tools, using Monte Carlo (MC) simulation. This progress has been achieved through inter-university collaboration and university-industry interaction. Over the extended period, driven by NCCE-sponsored workshops and extensive collaborations and benchmarking, a landmark MC calibration effort resulted in the publication titled: "A Comparison of Numerical Solutions of the Boltzmann Transport Equation for High-Energy Electron Transport Silicon" (A. Abramo et al, IEEE TED, vol. 41, #9, p. 1646, Sept. 1994). This paper and joint work set the stage for dramatic improvements in reliability of results and consistency in assumptions used by the community in using high-energy transport parameters and supporting fundamental semiconductor materials parameters.
In a related effort at Stanford, an improved model for impact ionization was achieved, using an extracted tail-electron distribution approach. Extensive use of and comparisons with MC analysis were a key part of the modeling efforts. Traditionally, the hot carrier effects, such as impact ionization, can only be modeled accurately using Monte Carlo method which is computationally expensive. On the other hand, some of the existing macroscopic models such as the lucky electron model have less accuracy. To resolve these drawbacks, we improved the lucky electron model using microscopic transport data derived from Monte Carlo simulation. The modeling approach is of hybrid nature in the sense of combining the original lucky electron model, which uses some fitting parameters, and tail-electron model. The preliminary results in simulating the impact ionization coefficients in bulk silicon have almost perfect match with the full band MC calculation. We are extending this analysis to actual devices. For further details, the IEEE EDL paper (Vo. 16, #1, p.26, Jan. 1995) as well as the PhD thesis authored by Chiang-Sheng Yao.
In the area of transport modeling at the partial differential equation (PDE) level to account for higher order hot carrier effects, there has been a progression of computational experiments with using higher moments of the Boltzmann Transport Equation (BTE). PhD Thesis work of Edwin Kan (U. of Illinois) was extended by Datong Chen, formulated into an Energy Transport (ET) form (following the original approach of R. Stratton circa 1962) and implemented in prototype versions of PISCES. Typical results can be found in IEEE EDL (vol. 13, #1, p. 26, 1992). The PISCES prototype was further extended to a two carrier version (2ET), was partially tested and documentation appeared in 1994. Unfortunately, the code was fragile due to a number of concurrent merges from other versions and was abandoned as an ongoing development platform. Another effort involved use of the hydrodynamic formulation of the BTE, including efforts at parallel computer implementation with support from DARPA. Results of this project both in terms of benchmark results and overall parallel efficiency can be found in IEEE CAD (vol 15, #9, p. 1029, Sept. 1996) and PhD Thesis work of Narayan Aluru.
The above efforts--ET, 2ET and HD--all demonstrated typical peaking effects in carrier velocities and direct means for extracting carrier temperatures. Nonetheless, to date there has been limited (if any) conclusive demonstration concerning the predictive accuracy of these (or equivalent) moment-based extensions of the BTE vis a vis the Monte Carlo method of solution. Nonetheless, there is still interest in alternative formulation of the HD, including possible extensions to account for quantum mechanical effects. One such effort is ongoing at the University of Texas, Austin where Prof. Graham Carey has implemented an HD formulation within the PROPHET simulation platform.
The Stanford efforts in advanced, PDE-based transport formulations is now ongoing as a sub-task under the DesCArtES project. Specifically, base on DARPA-funded efforts under the ParaSCOPE project (as well as the UT efforts cited above), PROPHET has been extended to include device simulation capabilities. Pioneering work by Mario Ancona at NRL has demonstrated a new Density Gradient (DG) formulation of the carrier transport equations that includes quantum mechanical corrections that can be implemented in multi-dimensions. In collaboration with Conor Rafferty (Bell Labs) and Zhiping Yu (Stanford), they have implemented the model in PROPHET, tested it for a number of interesting ultra-thin oxide MOS devices and extended the capabilities to include a tunneling model. Progress in developing and extending the DG model are reported in SISPAD (papers appear in 1997, 1998 and 1999).
For further discussion of the PDE-based model development activities, ongoing activities are covered in the report and final documentation of the ParaSCOPE project (DARPA funded) and ongoing model development activities under the DesCArtES project (NSF funded).