Stanford University has been at the forefront of Integrated Circuit (IC) modeling and simulation for nearly two decades. The research and development associated with programs such as SUPREM and PISCES has broadly supported both academic and industrial interest in technology modeling.
This year's meeting continues the presentation and consideration of important shifts in scope and content of the field of TCAD, both at Stanford and in the much broader context of the SIA Roadmap and other groups working in this field. The concepts of and initial efforts in creating a hierarchy of TCAD models that spans from atomic-scale process models through circuit level applications for TCAD will be presented. In the process and device modeling sessions, there will be increased consideration of the fundamental models used in tools such as SUPREM and PISCES, including calibration based on both experiments and deeper physical modeling techniques such as Monte Carlo and molecular dynamics. Trends in technology development, both core technologies (CMOS, Low Power...) and application "drivers" (Radio Frequency (RF), etc.), will be used to motivate discussion of modeling topics and as specific examples. Computational prototyping will be the other main focus of the meeting with balanced consideration given to: 1) examples that demonstrate how the concepts build on hierarchical TCAD and 2) the underlying software engineering and basic research issues needed to realize such systems.
The meeting format is a combination of lectures and demonstrations. Copies of speaker slides are provided for easy reference. Coffee breaks and meals as listed are included in the registration fee and provide an excellent opportunity to interact with speakers and other participants.
The first day's agenda focuses on process and device modeling, calibration of models, and TCAD tools that support new developments in the field. Both SRC- and ARPA-funded programs related to process and device modeling will be reviewed. After an overview of recent trends in modeling and general status of tools such as SUPREM and PISCES, in-depth presentations will address specific issues such as physical models and the creation of a modeling hierarchy. The discussion of hierarchical devices models is a research theme of growing importance within the National Center for Computational Electronics (NCCE) sponsored by NSF. The final set of talks in this session provide a very exciting and diverse set of applications for TCAD.
The second day shifts the emphasis to computational prototyping and applications for device, interconnect, and circuit modeling. The opening session will introduce the key concepts of new ARPA-funded efforts in this area. Building on many of the hierarchical TCAD concepts, the discussion shifts toward advanced software issues for computational prototyping. Issues related to device and interconnect scaling will be one unifying theme that demonstrates a range of complementary analysis methods. Advanced capabilities using FASTCAP and SAMPLE 3D will be one set of highlights in this session. Modeling and circuits issues related to mixed signal applications will be considered along with the recent developments in BSIM3. A key theme in several of the sessions relates to internet collaboration, including the growing use of the world-wide web (WWW). The day ends with a WWW-based set of demonstrations that will be available for browsing after the meeting.
Wednesday, August 9, 1995
8:00 a.m. Registration
Advanced Impurity Diffusion Modeling
8:30 Physical Models for Process Simulation Peter Griffin
9:10 Precipitation, Clustering and Bipolar Applications Paul Rousseau
9:35 Implant Damage and Transient Enhanced Diffusion Henry Chao
10:00 Transient Enhanced Diffusion and SOI Applications Scott Crowder
10:25 Break
Advanced Oxidation Modeling
10:50 Characterization of Thin Films--Nitrides, Oxides
and Polysilicon Charlie Yu
11:15 Experiments on Submicron Isolation Structures Peter Smeys
11:40 New Constitutive Model for Visco-Elastic Oxidation Vinay Rao
12:05 Lunch
Physical Models for Device Simulation
1:00 Hierarchical Device Modeling--from Quantum Transport
to Compact Models Edwin Kan
1:40 A Unified Consideration toward Macroscopic
Hot Carrier Modeling MOS Devices Chiang-Sheng Yao
2:05 Monte Carlo Simulation using Full Band
(DAMOCLES) and Reduced Band Models Gyo-Young Jin
2:30 Break
Technology Scaling--Applications of TCAD
2:50 CMOS Low-Power Design Using PROPHET and PADRE Aon Mujtaba
3:15 Characterization of ESD Devices and Protection
Circuits Stephen Beebe
3:40 Substrate Noise--Measurements and Modeling Bruce Wooley
4:15 Advanced Thermal Modeling for SOI Devices Ken Goodson
6:00 Dinner, Faculty Club
Thursday, August 10, 1995
Computational Prototyping--A Paradigm Shift
8:30 Computational Prototyping of 21st Century `
Semiconductors Bob Dutton
9:00 Assessing Advanced IC Technologies--Present
Capabilities and Future Needs James Chung
9:30 New Research Paradigm using Internet Collaboration Paul Losleben
10:00 Break
Tools for Computational Prototyping
10:20 Multi-Processor Device Simulation (PISCES-MP) Bruce Herndon
10:55 Framework-based Architecture of SUPREM OO7
(Object-Oriented) Zak Sahul
11:20 A Layered Model (Ala Mode) Approach for SUPREM
Modules Dan Yergeau
11:45 Centralized Geometry Services Using BTU Robert Wang
12:10 Lunch
Hierarchical Interconnect Modeling
1:00 Extraction for Interconnect Analysis Using SAMPLE 3D John Sefler
1:25 Tools for Interconnect--Delay and Signal Integrity
Analysis Jacob White
1:50 Devices and Interconnect Constraints Krishna Saraswat
2:15 Back-End Process Simulation Mike Deal
2:40 Break
Technologies for Wireless and Circuit Modeling
3:00 Circuit and Device Considerations for Wireless
Applications Tom Lee
3:40 Virtual Instrument Using PISCES--Harmonic Balance
and Mixed-Mode Boris Troyanovsky
4:05 BSIM3--SPICE Modeling for MOS Devices Chenming Hu
4:45 WWW-based Demos and Reception
Fee: The fee for each day is $250 including lecture notes, luncheon, and dinner (August 9, 1995) or $425 for attending both days. Enrollment is limited, and advance enrollment is required.
How to enroll: Please complete and return the registration form. Enrollment may be made by individuals or companies. Deadline for submission of enrollment forms: July 21, 1995.
Refunds: If you enroll and then cannot attend, a refund will be granted if requested in writing prior to August 1, 1995.
Housing: A block of rooms has been reserved at the Holiday Inn (415) 328-2800. Housing is also available on the Stanford campus residences at reasonable rates. Campus recreational facilities are available for your use. For further information, contact the Conference Office at 123 Encina Commons, Stanford, California, 94305-6020; telephone (415) 725-1429. A list of hotels and motels in the vicinity of Stanford University can be provided upon request.
For further information: Write or call Stanford University Integrated Circuits Laboratory, c/o Robert W. Dutton, AEL 202, Stanford, California 94305-4055; telephones (415) 723-1950 and 723-1349; FAX (415) 725-7731; or send e-mail to cad95@gloworm.stanford.edu.
REGISTRATION FORM:
Using your Web browser, print this page to your local printer, fill in
the form and mail to the address shown below. Deadline is July 21,
1995.
I enclose a check in the amount of ______ $_____ to cover ___ enrollment(s) in (check one) [ ] Wednesday August 9, 1995 ($250) [ ] Thursday August 10, 1995 ($250) [ ] Both Days August 9-10 1995 ($425) [ ] SRC Member/Government rate August 9-10, 1995($350) Name ___________________________________________________ Employed by ____________________________________________ Company address ________________________________________ Electronic mail address ________________________________ Daytime telephone and extension ________________________ Fax number _____________________________________________Make check payable to Stanford University, and send to
Professor Robert W. Dutton