Contractor: Stanford University
Agreement Number: F30602-96-2-0308
Project Number: HJ1500-3221-0599
DARPA Order Number: N-7-0504/AO E117/12
Contract Period: September 13, 1996 - September 12, 1999
Date: June 1, 1999
Sponsor: Department of the Air Force
Technical POC: Robert W. Dutton
Report Prepared by: Robert W. Dutton
Task 2
Task 3
Develop and demonstrate fully-integrated, FEM-based prototype solver capabilities to model behavior and fabrication process-dependency of MEMS devices. This will include capabilities to consider multi-physics and materials dependencies as well as other process induced factors--geometry effects due to deposition/etching. The overall tool integration strategy will be to develop and test key components that overcome limits currently seen to be "bottlenecks" in commercial systems. Application-specific lumped modeling will be developed and used to guide the overall direction of the CAD efforts, including improved parameter extraction schemes that cross-link device performance with layout parameters that can in turn support design (and hopefully optimization) of practical MEMS devices (i.e., RF switch).
Approach:
Progress:
A novel actuator that can travel stably beyond one-third of the initial gap (a trademark limitation of conventional actuators) has been demonstrated. A "folded capacitor" design requiring only minimal modifications to the layout of conventional devices, reduces the parasitic capacitances and modes of deformation that limit performance. A device fabricated in MUMPs, useful for optical applications, can travel twice the conventional range before succumbing to a tilting instability.
Additional measurements show that the influence of gold on polysilicon film thickness, average stress and stress gradient depends on the relative area of the gold with respect to the area of exposed polysilicon. This can be a significant source of design-dependent nonuniformity among nominally similar devices. This effect has not been previously observed. We believe the change in stress conditions is due to the etching of the polysilicon surfaces which have different stresses than the middle of the polysilicon layers. Also, the upper surfaces are exposed for a longer time to the HF etch and hence etch more. This provides some insight into the stress variation through the thickness of the polysilicon layer.
Capacitance-voltage measurements of untethered plates resting on the nitride surface indicate that the total effective gap between the plates and the substrate decreases with increasing voltage. The exact mechanism is difficult to determine although interferometric measurements support the notion that the contact surfaces are compressing.
A web site describing the canonical test problem, complete with measurement data [2], simulation decks and mask information is being set up.
In the area of geometry, progress continues to be made utilizing the domain decomposition technique [3]. For a given deposition step in the initial algorithm, every 1-D, 2-D, and 3-D region was created separately as a solid object and then the final layer was created by unioning all of the individual solids together. The major motivation for this was the easy of implementation, but problems exist if the solids do not match up cleanly at the interfaces of the different dimensional regions. For example, if different numerical solution techniques are used in the 2-D regions than in the 3-D regions, this can lead to small numerical discrepancies in the deposition thickness at the interface. Such artificial geometric features are difficult to eliminate at the meshing stage, and cause unnecessary mesh density. This has motivated an algorithm developed to stitch together the top surfaces created in the different regions, and then create the solid from the resulting surface. This method allows enforcement of continuity between regions, eliminates unnecessary artificial perturbations in the data, and reduces the number of solid modeling union operations needed to construct a given layer. The beta code for the stitching algorithm is in place, however, additional problems in the current solid modeling kernel being used (Shapes, by XOX) have arisen due to the poor quality (high aspect ratios) of the stitched surface discretization. In an attempt to improve the initial surface discretization, two decimation algorithms were tried (vtkDecimate in the Visualization Toolkit and utilities in MEGA from RPI). Neither produced satisfactory results, motivating the search for methods to create better surface discretizations in the regions prior to the stiching process.
Difficulties/Problems:
Develop extraction schemes for materials properties using simplified MEMS test structures. In combination with the CAD tools efforts, the physical models (including microstructure) will be evaluated and modified as needed. The scope of material characterization efforts include both standard metal layers (possibly graded as well) and reliability issues such as plastic yield and fatigue. The extraction and validation steps for physical models is a key linking between the three sub-tasks.
Approach:
Progress: 1. Fatigue Study
Modeling of the displacement distribution within the micromechanical testing system has been performed. This analysis allows the determination of strain correction factors for different sample thicknesses. The knowledge of these strain correction factors enables the calculation of the actual strain within the gage section from the measured piezo displacement. All previously recorded data, which has been reported in terms of piezo displacement, can now be recalibrated to strain. Thus comparisons of the measured results to literature data is now possible.
Tensile tests on aluminum microbeams of four thicknesses have been performed at strain rates between 7.6x10^-2/s and 7.6x10^-6/s. Strain rate sensitivity has been observed for all film thicknesses. Results for small strain rates in the nominally linear-elastic regime (at small strains) deviate considerably from linear elastic behavior. The observed characteristics are well described by anelastic material behavior. Anelastic reloading after stress relaxation experiments supports the anelasticity hypothesis.
TEM analysis of cyclically loaded samples revealed the evolution of the dislocation arrangement with the number of loading cycles. At first dislocations interact and entangle; later they form dislocation networks within a grain. Upon further cycling this dislocation network expands and eventually reaches across multiple grains.
2. In-situ Stress Measurement
Fabrication of the first generation of dedicated stress measurement sensors has been completed.
The dedicated stress measurement sensor comprises two levels, i.e. the Membrane-Wafer and the Tip-Wafer. Both are single polished silicon wafers, 4", <100> oriented, lightly-doped, and 500 (m thick. We started processing with a batch of six wafers per level.
For the Membrane-Wafer, we first defined corrugation rings on four of the Membrane-Wafers by plasma etching silicon. The corrugations were initially designed to ensure sufficient flexibility of the deflection membrane to achieve a reasonably low deflection voltage (<100V) for tunneling. However, the corrugations also make the membrane more fragile and the membrane surface uneven. For comparison, we left two Membrane-Wafers without corrugation rings. We then grew 0.5 um of LPCVD silicon nitride on both sides of the Membrane-Wafer, and plasma etched the backside nitride (PR as masking layer) to define the deflection-membrane-mask. To release the front side nitride membrane, we used KOH (backside nitride as mask) to etch all the way through the wafer. We are currently using 0.5 um of low stress silicon nitride as the deflection membrane. The thickness and initial stress of the membrane can be altered by varying the fabrication conditions. Thus deflection membranes with different mechanical properties can be produced for measuring different levels of stress change.
For the Tip-Wafer, we first grew 0.5 um of thermal oxide on both sides and patterned the front side oxide by Buffered Oxide Etch (BOE) to define the tip-mask. We then grew 0.5 um of LPCVD silicon nitride on both sides, and plasma etched the backside nitride (PR as masking layer) to define the vent-hole-mask. From the backside, we etched all the way through the wafer (backside nitride as mask) by KOH to form the vent hole. On the front side, we etched silicon about 10 um down by KOH to form the tip. After stripping the oxide masking layer by BOE, we did a tip-rounding step, i.e. 1.5 um of thermal oxide was grown and then stripped off. Undercutting of silicon from the previous KOH etching may cause the top of the tip to be mushroom-shaped underneath the tip-mask. Tip-rounding ensures that any unwanted top part of the tip is oxidized and removed. The tip shape is thus well defined. Afterwards, we grew another 1.5 um of oxide on the Tip-Wafer, which serves as the passivation layer. To define the electrodes and the bond rings, we evaporated Cr/Pd/Au on the front sides of both the Membrane-Wafer and the Tip-Wafer and patterned the metals.
Difficulties/Problems:
Design and implementation of MEMS structures, including materials parameter extraction, will be used to test the CAD and physical models based on MEMS devices of interest to DARPA. The experimental measurements made with these structures will facilitate the critical evaluation of models, physical parameters and overall simulation accuracy of CAD for MEMS devices. The test vehicles from this work also support canonical benchmarking of both new materials for MEMS and accuracy of Composite CAD in MEMS applications, specifically the RF switch.
Approach:
Progress:
Attempts over the last half-year to wrestle single film membranes (with Ir,W and Mo) into a useful RF MEMS process have been frustrated by a number of process integration issues and the control of film stress gradients during deposition . The tool to help manage these stress gradients within the deposited films requires an in situ real-time stress measurement tool that is being developed but won't be available for testing for several more months (mid to late summer 1999). If the proposed in situ stress measurement test structure works as well as we anticipate, we can begin testing again the deposition parameters that will yield null or slightly net tensile stress gradients for these films. This work is still of considerable interest to the general MEMS community and the Subtask #3 group will continue to pursue these film deposition monitoring methods in the future.
Our lack of immediate success for the single layer metal RF MEMS switch, has not deterred us from devising a process that uses multi-layered (or composite) films. The materials used are thin encapsulating films of Al layered both above and below a mechanically stiff layer of either PECVD silicon nitride, or sputtered layers of Ti/W or Si. Using this approach we successfully demonstrated a MEMS device (an accelerometer) that is identical in structure to the RF MEMS Switch. This composite film approach was initially put aside as it was determined to be a much more difficult structure to model. Now, given the process difficulties outlined above and our success with the Accelerometer MEMS device we have returned to this approach to complete an RF MEMS switch. From the modeling (and measurement) point of view, the new composite films still use Aluminum layers for the hinges, hence the detailed characterization and modeling efforts related to fatigue in Al films is directly relevant to to ongoing developments of a composite material RF MEMS switch.
Difficulties/Problems:
Technology Transfer:
An RF MEMS switch, designed by the Kovacs group collaboratively with AFRL, Hanscomb AFB, now includes a similar effort with Hughes Electronics/Raytheon research labs in Malibu CA. All layouts also include a subset of the Testarosa mechanical test structures which continue to be a boon for process control and characterization. These switches will be built onto Sapphire substrates and eventually integrated into our successful Silicon On Sapphire/CMOS (SOS-CMOS) process, which we have developed for high voltage circuits (up to 300V on chip from 5V power supply) and photovoltaic arrays that could potentially be used to drive the MEMS switches with only light supplied as power. This indicates that a completely integrated device using only light for input power could be used to operate these RF MEMS switches. We are currently working on further collaborations with them.
II. Financial Information: AF F30602-96-2-0308
| Total Amount Funded | $2,378,700 | |
| Salaries and Wages | $589,304 | |
| Staff Benefits | 94,478 | |
| Travel | 30,730 | |
| Expendable Mat./Services | 186,868 | |
| Repairs and Maintenance | 19,693 | |
| -------- | ||
| Total Direct Costs | $921,073 | |
| Capital Equipment | 128,593 | |
| Student Aid (Tuition) | 100,349 | |
| Indirect Costs | 502,914 | |
| Total Expenses to date | $1,652,929 | |
| ---------- | ||
| Funds to date, 3/31/99 | $ 725,771 | |