Eric Tse received his BS in Electrical Engineering from the University of California at Berkeley in 1992. He is currently working towards a MS degree. He has been working for Technology Modeling Associate (TMA) since June 1993.

His research focus is on TCAD system integration, Wafer structure modeling using SWR (semiconductor wafer representation. He is a member of the Asian Business League (93-94) of Stanford University. He honors include: Honorary Scholarship (90-91), U.C. Berkeley, Honor Roll (89-92), U.C. Berkeley, Marin County Athletic Scholarship (90-91), U.C. Berkeley. His hobbies include: Playing tennis, squash and ping-pong.

Eric Tse(tse@gloworm.Stanford.EDU)
AEL 229
Integrated Circuits Laboratory
Stanford University
Stanford, CA 94305-4055