Hwasik Park
Hwasik Park received his B.S. and M.S. degrees in electronic engineering
and Ph.D. degree in semiconductor engineering from
Chung Ang University,
Seoul, Korea, in 1984, 1986, and 1993 respectively.
He worked on telecommunication technology for Korea Telecom Research
Center, Seoul, Korea, from 1986 to 1989, and was with IBM Thomas J. Watson
Research Center, Yorktown Heights, NY, from May 1991 to August 1991,
where he worked on HBT process simulation as a research fellow. Since
1993, he has been with Stanford University where he is working on
three-dimensional silicon process modeling and simulation as a
postdoctoral research affiliate.
He is a member of IEEE, Korea Institute of Electronics Engineering(KIEE)
and Korean Vacuum Society.
Current Research : 3D LOCOS Modeling
Research Interests
- 3D Monte-Carlo Simulation of Ion Implantation
- 3D Oxidation Simulation
- Extrinsic/Coupled Diffusion Physics and Modeling
- TCAD Framework
- Equipment Modeling and Design
Major Publications
- Hwasik Park, A Study on the MOSFET Modeling using Boundary
Element Method, M.S. Thesis, Chung Ang University, Seoul, Korea, Feb.
1986.
- Hwasik Park, Donghwa Yu, Youngjin Song, Hojung Hwang," A Study on
the Simulation of Interconnection Capacitance Caculation for VLSI," J.
KIEE, Vol.29-B, No.1, pp.25-32, Jan. 1992.
- Hyunwook Song, Hwasik Park, et al,"Development of Simulator for the
Design of Optimal FIB Lens Structure," J. Korean Vacuum
Society, Vol.1, No.2, pp.269-276, Feb. 1992.
- Hwasik Park, Hojung Hwang," Development of Two-dimensional Silicon
Oxidation Simulator using SVP Algorithm," J. KIEE, Vol. 29-A,
No.12, pp.101-109, Dec. 1992.
- Hwasik Park, Multi-dimensional Effects in ULSI Semiconductor
Process - Theory and Simulation, Dissertation, Chung Ang Univ., 1993
- Hwasik Park, Junha Lee, Hojung Hwang," Three-dimensional Ion
Implantation Simulator using Analytical Models," J. KITE, Dec.
1993.
- Hwasik Park, Peter Smeys, Peter Griffin, Zakir H. Sahul,
Krishna C. Saraswat, Robert W. Dutton, and Hojung Hwang,
"Quasi-3D Modeling of Sub-Micron LOCOS Structures," IEEE Trans. on
Semiconductor Manufacturing, Nov. 1995, will be published.
Hwasik Park (hspark@gloworm.Stanford.EDU)
AEL 209
Integrated Circuits Laboratory
Stanford University
Stanford, CA 94305-4055