Francois Clement

Studies

1995

Cours d'utilisateur avancé pour l'environnement de programmation Softbench, Hewlett-Packard, Genève

1993

Intensive Summer Course on Low-Noise in Analog and Mixed- Mode IC Design, Ecole Polytechnique Fédérale de Lausanne (Lausanne)

1992

Intensive Summer Course on CMOS & BiCMOS VLSI Design, Ecole Polytechnique Fédérale de Lausanne (Lausanne)

Graduate:

1993-1995

Ph.D. in Electrical Engineering: Swiss Federal Institute of Technology (Lausanne)

1987-1991

Electrical Engineering: Swiss Federal Institute of Technology (Lausanne)

Under Graduate:

1984-1987

Electrical Engineering: Engineering School of Fribourg (Fribourg)

Apprenticeship:

1981-1984

Professional School (Fribourg)

Secondary School:

1978-1981

Cycle d'Orientation de Marly (Marly)

Primary School:

1972-1978

Ecole primaire de Marly-Cité (Marly)

Professional Activities

1. February 1991: Reasearch Assistant at the Electronic Labs (LEG) of the Swiss Federal Institute of Technology (EPFL), Lausanne.
2. October 1993: Computer System Manager at the LEG, EPFL, Lausanne.
3. January 1995 - April 1995: Digital Electronic Teacher at the Engineer School of State Vaud (EINEV), Yverdon.
4. November 1992 - April 1993: Teacher for the Electronic Practical Laboratory at the Engineer School of Fribourg (EIF) à Fribourg.
5. November 1989 - November 1990: Développement d'un système de base de données pour la gestion des étudiants, EIF, Fribourg.

Publications

1. M. Declercq, M. Schubert and F. Clément, "5V-to-75V CMOS Output Interface Circuits," In proceedings of the International Solid-State Circuits Conference, pp. 10.6.1-4. IEEE, San Francisco, 1993.
2. M. Declercq, F. Clément, M. Schubert, A. Harb and M. Dutoit, "Design and Optimization of High-Voltage CMOS Devices Compatible with a Standard 5V CMOS Technology," In proceedings of the Custom Integrated Circuits Conference, pp. 24.4.1-4. IEEE, San Diego, 1993.
3. F. J. R. Clément, E. Zysman, M. Kayal and M. Declercq, "LAYIN: Toward a Global Solution for Parasitic Coupling Modeling and Visualization, " In proceedings of the Custom Integrated Circuits Conference, pp. 24.4.1-4. IEEE, San Diego, 1994.
4. F. J. R. Clément, E. Zysman, M. Kayal and M. Declercq, "LAYIN: LAYout INspection CAD Tool Dedicated to the Parasitic Coupling Effects through the Substrate of Integrated Circuits," In proceedings of the PATMOS (Power And Timing Modelization, Optimization and Simulation) Conference, pp. 267-276. bis, Oldenburg, 1995.