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This workshop is co-sponsored by universities within the NSF DesCArtES and NASA/Ames Research Center. It is a continuation of the dialog developed over the past decade in the area of Computational Electronics initiated by the NSF-sponsored NCCE and more recently promoted by co-sponsored workshops held at NASA/Ames. The following are session titles and panelists in the four areas targeted for discussion at the workshop. The format will be targeted at presenting themes and hopefully controversial issues being faced in each of these areas:

1. Model requirements & challenges between process-device-circuit levels: Panelists--
   • M. Miura-Mattausch, Hiroshima University, Panel Chairperson
   • C. McAndrew, Motorola
   • K. Mayaram, Oregon State University
   • K. Green, Texas Instruments
2. Benchmarking progress in scaling and modeling (i.e.Well-Tempered MOS): Panelists--
   • M. Ieong, IBM, Panel Chairperson
   • D. Antoniadis, MIT
   • U. Ravaioli, University of Illinois
   • C. Dachs, Philips
3. Quantum effects and limits in device scaling: Panelists--
   • M. Lundstrom, Purdue University, Panel Chairperson
   • B. Meinerzhagen, U. Bremen, Germany
   • A. Abramo, U. Udine, Italy
   • A. Anantram, NASA/Ames
   • N. Sano, Tsukuba University, Japan
4. Scaling limits of devices and modeling: Panelists--
   • C. Rafferty, Lucent Technologies, Panel Chairperson
   • D. Vasileska, Arizona State University
   • S. Banerjee, University of Texas, Austin
   • E. Kan, Cornell University

The area of computational electronics and the community of collaborators has grown steadily over the past decade. International events such as IWCE (International Workshop on Computational Electronics) and the sustained efforts supported by NSF under NCCE (National Center for Computational Electronics) and now DesCArtES (Distributed Center for Advanced Electronic Simulation) have promoted an active dialog with several important contributions. For example, the calibration of physical coefficients for Monte Carlo (MC) simulations and collaborative benchmarking (Abramo, et. al., "A Comparison of Numerical Solutions of the Boltzmann Transport Equation for High-energy Electron Transport Silicon," IEEE Transactions on Electron Devices, 1994) has provided common understanding and improved overall quality of published results based on MC. Also, more recently the sharing of device design information for a set of "Well-tempered MOSFETs" has promoted the benchmarking of various modeling formulations on well-defined structures.

GENERAL INFORMATION

Registration Information: The registration fee is $115 (includes continental breakfast, coffee breaks, and lunch). Enrollment is limited, and advance enrollment is required. To register, fill out the registration form and mail the form and payment by August 24, 2000. Please send checks and registration forms to:

c/o Fely Barrera
CISX 332
Stanford University
Stanford, CA 94305-4075

Checks must be made payable to Stanford University and drawn from a US bank. Credit card payment is not accepted. Cash and Traveler's Checks are accepted onsite only. Request for cancellation must be received by August 25, 2000 to qualify for a refund.

Hotel: A block of rooms has been reserved at the Seattle Sheraton Hotel and Towers, 1400 Sixth Avenue, Seattle, WA (206) 447-5555, fax (206) 621-8441 under SISPAD 2000.

For further information, please contact: Fely Barrera, CISX 332, Stanford University, Stanford, California 94305-4075; telephone (650) 723-1349; FAX (650) 725-7731; email: fely@ee.stanford.edu.

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