September
9-11, 2009 — Hotel Del Coronado — San Diego — California
TECHNICAL PROGRAM
The 2009 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD '09) will be held on September 9-11, 2009 at Hotel del Coronado, San Diego, California.
September 8, 6:00pm - 8:00pm
September 9, 7:30am - 2:00pm
Wednesday, September 9
8:30 - 8:45
Opening Remarks Karti Mayaram, Oregon State University
Plenary Session
8:45 - 9:30 I-1
"Technology Projection Using Simple Compact Models" H.-S. P. Wong, Stanford University
9:30 - 10:15 I-2
"Atomic Scale Simulation of Interface and Surface Phenomena during Thin Film Growth" K.-R. Lee, KIST
Break (15 minutes)
10:30 - 11:15 I-3
"Overview of Modeling Approaches for Scaled Non Volatile Memories" D. Ielmini, Politecnico di Milano
11:15 - 12:00 I-4
"TCAD for Power Devices" G. Wachutka, TU Munich
Session 1 - Novel Devices
1:30 - 1:55 1-1
"Conductivity Mismatch and Voltage Dependence of Magnetoresistance in a Semiconductor Spin Injection and Detection Structure"
A. M. Roy, D. E. Nikonov*, K. Saraswat
Stanford University, Stanford, CA, *Intel Corporation,
Santa Clara, CA
1:55 - 2:20 1-2
"Lateral Ge/SiGe/Si Hetero-Channel p-type MOSFETs"
C.-Y. Chen, Y. Liu, J. Kim, R. W. Dutton
Stanford University, Stanford, CA
2:20 - 2:45 1-3
"A Low Voltage Steep Turn-off Tunnel Transistor Design"
P. Patel, K. Jeon, A. Bowonder, C. Hu
University of California, Berkeley, CA
2:45 - 3:10 1-4
"On the Feasibility of 500 GHz Silicon-Germanium HBTs"
A. Pawlak, M. Schroter*, J. Krause, G. Wedel, C. Jungemann**
Dresden University of Technology, Dresden, Germany,
*University of California, San Diego, CA, **University of Armed
Forces, Neubiberg, Germany
Session 2 - Memory
1:30 - 1:55 2-1
"Scalability Study of Floating Body Memory Cells"
A. Schenk
ETH Zurich, Zurich, Switzerland
1:55 - 2:20 2-2
"Characteristics of the Capacitorless Double Gate Quantum Well Single Transistor DRAM"
M. G. Ertosun, K. C. Saraswat
Stanford University, Stanford, CA
2:20 - 2:45 2-3
"Full 3D Simulation of 6T-SRAM Cells for the 22nm Node"
C. Shin, Y. Tsukamoto*, X. Sun, T.-J. K. Liu
University of California, Berkeley, CA, *Renesas Technology
Corp., Itami, Japan
2:45 - 3:10 2-4
"Convex Channel Design for Improved Capacitorless DRAM Retention Time"
M. H. Cho, C. Shin, T.-J. K. Liu
University of California, Berkeley, CA
Session 3 - Stress Effects
3:30 - 3:55 3-1
"Hole Mobility and its Enhancement with Strain for Technologically Relevant III-V Semiconductors"
A. Nainani, D. Kim, T. Krishnamohan, K. Saraswat
Stanford University, Stanford, CA
3:55 - 4:20 3-2
"Thickness Dependence of the Effective Masses in a Strained Thin Silicon Film"
V. Sverdlov, O. Baumgartner, T. Windbacher, F. Schanovsky,
S. Selberherr
TU Wien, Vienna, Austria
4:20 - 4:45 3-3
"Monte Carlo-Based Analytical Models for Electron and Hole Electrical Parameters in Strained SiGeC Alloys"
M. Michaillat, D. Rideau, F. Aniel*, C. Tavernier, H. Jaouen
STMicroelectronics, Crolles, France, *Universite Paris-Sud,
Orsay, France
4:45 - 5:10 3-4
"Strain Dependence of Dielectric Properties and Reliability of High-k Thin Films"
K. Suzuki, K. Imasaki, Y. Ito, H. Miura
Tohoku University, Sendai, Japan
Session 4 - Quantum Effects
3:30 - 3:55 4-1
"Resonant Injection Enhanced Field Effect Transistor for Low Voltage Switching: Concept and Quantum Transport Simulation"
H. Chen, L. F. Register, S. K. Banerjee
University of Texas at Austin, Austin, TX
3:55 - 4:20 4-2
"Investigation of In_xGa_{1-x}As Ultra-Thin-BodyTunneling FETs using a Full-Band and Atomistic Approach"
M. Luisier, G. Klimeck
Purdue University, West Lafayette, IN
4:20 - 4:45 4-3
"Dependence of Injection Velocity and Capacitance of Si Nanowires on Diameter, Orientation, and Gate Bias: An Atomistic Tight-Binding Study"
N. Neophytou, G. Klimeck*, H. Kosina, S. Selberherr
TU Wien, Vienna, Austria, *Purdue University, West Lafayette,
IN
4:45 - 5:10 4-4
"Using Density-Gradient Theory to Model Sb-Based p-Channel FETs"
M. G. Ancona, J. B. Boos, B. R. Bennett
Naval Research Laboratory, Washington, DC